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Patent # Description
2016/0204260 STRUCTURE AND FORMATION METHOD OF FINFET DEVICE
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a...
2016/0204259 HIGH EFFICIENCY FINFET DIODE
Disclosed are methods to form a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from...
2016/0204258 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
To improve performance of a semiconductor device. Over a semiconductor substrate, a gate electrode is formed via a first insulating film for a gate insulating...
2016/0204257 SELF-ALIGNED CONTACT PROCESS ENABLED BY LOW TEMPERATURE
Self-aligned contacts of a semiconductor device are fabricated by forming a metal gate structure on a portion of a semiconductor layer of a substrate. The...
2016/0204256 METHODS OF FORMING DISLOCATION ENHANCED STRAIN IN NMOS STRUCTURES
Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include...
2016/0204255 METHOD OF MAKING A FINFET, AND FINFET FORMED BY THE METHOD
A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between,...
2016/0204254 SEMICONDUCTOR DEVICE
A semiconductor device includes a hetero junction structure including an electron transport layer of GaN and an electron supply layer of ...
2016/0204253 III-V MOSFET WITH STRAINED CHANNEL AND SEMI-INSULATING BOTTOM BARRIER
Embodiments include a method for fabricating a semiconductor device and the resulting structure comprising forming a semi-insulating bottom barrier on a...
2016/0204252 SEMICONDUCTOR DEVICE
A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface...
2016/0204251 PILLAR-SHAPED SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR
A SiO.sub.2 layer is formed at a middle of a Si pillar. An opening is formed in a gate insulating layer and a gate conductor layer in a peripheral portion that...
2016/0204250 NEW LAYOUT FOR LDMOS
A layout structure, a semiconductor device and an electronic apparatus are provided. The layout structure includes at least one LDMOS. The LDMOS includes a...
2016/0204249 MOSFET Having Dual-Gate Cells with an Integrated Channel Diode
A semiconductor device includes MOSFET cells having a drift region of a first conductivity type. A first and second active area trench are in the drift region....
2016/0204248 SEMICONDUCTOR DEVICE WITH VERTICAL GATE AND METHOD OF MANUFACTURING THE SAME
A gate electrode is formed in a trench reaching a drain region so as to leave a concave portion on the top of the trench. A first insulating film is formed,...
2016/0204247 METHOD FOR FABRICATING A METAL HIGH-K GATE STACK FOR A BURIED RECESSED ACCESS DEVICE
A method for fabricated a buried recessed access device comprising etching a plurality of gate trenches in a substrate, implanting and activating a...
2016/0204246 Ge and III-V Channel Semiconductor Devices having Maximized Compliance and Free Surface Relaxation
Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel...
2016/0204245 PROTECTION LAYER ON FIN OF FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE
A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from...
2016/0204244 SEMICONDUCTOR DEVICE AND METHOD OF MAKING SAME
A semiconductor device and method of forming the same is described. In an example, a polysilicon layer is deposited on a substrate having at least one...
2016/0204243 SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier...
2016/0204242 COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
An embodiment of a compound semiconductor device includes: a substrate; a nitride compound semiconductor stacked structure formed on or above the substrate;...
2016/0204241 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a first semiconductor layer formed of a nitride semiconductor on a substrate, a second semiconductor layer formed of a nitride...
2016/0204240 POWER SEMICONDUCTOR DEVICE
A power semiconductor device is provided comprising: a collector electrode, a collector layer of a second conductivity type, a drift layer of a first...
2016/0204239 INSULATED GATE POWER DEVICE USING A MOSFET FOR TURNING OFF
An insulated gate turn-off (IGTO) device has a PNPN layered structure so that vertical NPN and PNP transistors are formed. Trench gates are formed extending...
2016/0204238 IGBT Having Deep Gate Trench
There are disclosed herein various implementations of an insulated-gate bipolar transistor (IGBT) with buried depletion electrode. Such an IGBT may include a...
2016/0204237 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed...
2016/0204236 SEMICONDUCTOR DEVICE
A semiconductor device includes: a first conductivity-type collector region; a second conductivity-type field stop region disposed on the collector region; a...
2016/0204235 BIPOLAR TRANSISTOR, SEMICONDUCTOR DEVICE, AND BIPOLAR TRANSISTOR MANUFACTURING METHOD
Disconnection of a base line is suppressed even when a short-side direction of a collector layer is parallel to crystal orientation [011]. A bipolar transistor...
2016/0204234 BIPOLAR TRANSISTOR WITH CARBON ALLOYED CONTACTS
A method for forming a bipolar junction transistor includes forming a collector intrinsic region, an emitter intrinsic region and an intrinsic base region...
2016/0204233 INTEGRATED CIRCUIT HEAT DISSIPATION USING NANOSTRUCTURES
An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature...
2016/0204232 MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE
The semiconductor device is manufactured through the following steps: after first heat treatment is performed on an oxide semiconductor film, the oxide...
2016/0204231 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor...
2016/0204230 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
A method for fabricating semiconductor device is disclosed. Preferably, two hard masks are utilized to define the width of the first gate (may serve for a...
2016/0204229 Formation of Dislocations in Source and Drain Regions of FinFET Devices
Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and...
2016/0204228 METHOD FOR FORMING A NANOWIRE STRUCTURE
Embodiments of the invention describe a method for forming a nanowire structure on a substrate. According to one embodiment, the method includes a) depositing...
2016/0204227 Apparatus and Method for Power MOS Transistor
A method comprises providing a substrate with a second conductivity type, growing a first epitaxial layer having the second conductivity type, growing a second...
2016/0204226 STRESS MODULATION IN FIELD EFFECT TRANSISTORS IN REDUCING CONTACT RESISTANCE AND INCREASING CHARGE CARRIER MOBILITY
Field-effect transistor and method of fabrication are provided for, for instance, providing a gate structure disposed over a substrate. The fabricating method...
2016/0204225 FINFET WITH REDUCED CAPACITANCE
A method including depositing a gap fill material on top of a conformal dummy gate oxide above and in between a plurality of fins, forming one or more openings...
2016/0204224 TUNNEL FIELD-EFFECT TRANSISTOR, METHOD FOR MANUFACTURING SAME, AND SWITCH ELEMENT
A tunnel field-effect transistor (TFET) is configured by disposing a III-V compound semiconductor nano wire on a (111) plane of a IV semiconductor substrate...
2016/0204223 HIGH VOLTAGE DEVICE FABRICATED USING LOW-VOLTAGE PROCESSES
A method for fabricating a high-voltage transistor on a semiconductor substrate includes defining and forming shallow trench isolation regions for all of the...
2016/0204222 Growth of High-Performance III-Nitride Transistor Passivation Layer for GaN Electronics
Methods for forming a high-quality III-nitride passivation layer on an AlGaN/GaN HEMT. A III-nitride passivation layer is formed on the surface of an AlGaN/GaN...
2016/0204221 BOTTOM-UP METAL GATE FORMATION ON REPLACEMENT METAL GATE FINFET DEVICES
A method of fabricating a replacement metal gate in a transistor device, a fin field effect transistor (finFET), and method of fabricating a finFET device with...
2016/0204220 METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE
A method for manufacturing a silicon carbide semiconductor device includes steps of preparing a silicon carbide substrate having a first main surface and a...
2016/0204219 SEMICONDUCTOR DEVICE COMPRISING FERROELECTRIC ELEMENTS AND FAST HIGH-K METAL GATE TRANSISTORS
A semiconductor device comprises a first and second circuit element. The first circuit element comprises a first electrode structure including a first high-k...
2016/0204218 SEMICONDUCTOR STRUCTURE COMPRISING AN ALUMINUM GATE ELECTRODE PORTION AND METHOD FOR THE FORMATION THEREOF
An illustrative method includes providing a semiconductor structure. The semiconductor structure includes an active region and an electrically insulating...
2016/0204217 DEVICES WITH FULLY AND PARTIALLY SILICIDED GATE STRUCTURES IN GATE FIRST CMOS TECHNOLOGIES
A semiconductor product with certain devices having a first device with a fully silicided (FuSi) gate and a second device with a partially silicided gate is...
2016/0204216 DISPLAY DEVICE, ARRAY SUBSTRATE, AND THIN FILM TRANSISTOR
A method for manufacturing the thin film transistor, including: forming a gate, an active layer and a gate insulating layer disposed between the gate and the...
2016/0204215 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A Fin FET semiconductor device includes a fin structure extending in a first direction and extending from an isolation insulating layer. The Fin FET device...
2016/0204214 ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE
An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes...
2016/0204213 SEMICONDUCTOR DEVICE
A semiconductor device according to an embodiment switches high-frequency signals and includes a semiconductor layer of a first conductivity type. A first...
2016/0204212 SILICON NANO-TIP THIN FILM FOR FLASH MEMORY CELLS
A quantum nano-tip (QNT) thin film, such as a silicon nano-tip (SiNT) thin film, for flash memory cells is provided to increase erase speed. The QNT thin film...
2016/0204211 SELF-LIMITING SILICIDE IN HIGHLY SCALED FIN TECHNOLOGY
A method of forming a metal semiconductor alloy on a fin structure that includes forming a semiconductor material layer of a polycrystalline crystal structure...
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