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Patent # Description
2016/0204110 METHODS OF FORMING BURIED VERTICAL CAPACITORS AND STRUCTURES FORMED THEREBY
Methods of forming passive elements under a device layer are described. Those methods and structures may include forming at least one passive structure, such...
2016/0204109 SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
A semiconductor device includes an interlayer insulating film formed on a substrate and including a trench, a gate insulating film formed in the trench, a work...
2016/0204108 CMOS TRANSISTOR, SEMICONDUCTOR DEVICE INCLUDING THE TRANSISTOR, AND SEMICONDUCTOR MODULE INCLUDING THE DEVICE
Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include...
2016/0204107 SEMICONDUCTOR INTERGRATED CIRCUIT AND LOGIC CIRCUIT
Disclosed herein is a driver circuit including first and second n-channel transistors connected together in series between first and second nodes. The first...
2016/0204106 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a fin which comprises long sides and a first short...
2016/0204105 METHOD AND DEVICE FOR A FINFET
A method of forming a semiconductor device includes providing a semiconductor substrate. The semiconductor substrate includes a plurality of fins formed...
2016/0204104 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES
A semiconductor integrated circuit device may include a standard cell region on a surface of a substrate and a first active region on the surface of the...
2016/0204103 SEMICONDUCTOR DEVICE STRUCTURE
A semiconductor device structure having at least one thin-film resistor structure is provided. Through the metal plug(s) or metal wirings located on different...
2016/0204102 THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A three-dimensional (3D) semiconductor device is provided, comprising a substrate having a staircase region comprising N steps, wherein N is an integer one or...
2016/0204101 HIGH CURRENT, LOW SWITCHING LOSS SiC POWER MODULE
A power module includes a housing with an interior chamber and multiple switch modules mounted within the interior chamber of the housing. The switch modules...
2016/0204100 SEMICONDUCTOR DEVICE AND FORMATION METHOD THEREOF
The present disclosure provides a semiconductor device and formation method thereof. A shallow trench isolation structure is formed in a semiconductor...
2016/0204099 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power...
2016/0204098 GATE DIELECTRIC PROTECTION FOR TRANSISTORS
At least one method, apparatus and system disclosed herein involves forming a device comprising a transistor comprising an active gate and at least one...
2016/0204097 Semiconductor Device Having Overload Current Carrying Capability
A semiconductor device includes a semiconductor region having charge carriers of a first conductivity type, a transistor cell in the semiconductor region, and...
2016/0204096 LOW LEAKAGE BIDIRECTIONAL CLAMPS AND METHODS OF FORMING THE SAME
Low leakage bidirectional clamps and methods of forming the same are provided. In certain configurations, a bidirectional clamp includes a first p-well region,...
2016/0204095 SEMICONDUCTOR DEVICE
A first impurity diffusion region is provided within a semiconductor substrate, a second impurity diffusion region is provided within the first impurity...
2016/0204094 DISPLAY PANEL
A display panel including a plurality of sub-pixel groups arranged repeatedly to form a pixel array. Each of the sub-pixel groups includes a plurality of first...
2016/0204093 FABRICATION METHOD OF SEMICONDUCTOR PACKAGE
A fabrication method of a semiconductor package is disclosed, which includes the steps of: disposing a plurality of first semiconductor elements on an...
2016/0204092 SEMICONDUCTOR DEVICE
The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an...
2016/0204091 INVERTED OPTICAL DEVICE
Inverted optical device. In accordance with an embodiment of the present invention, a plurality of piggyback substrates are attached to a carrier wafer. The...
2016/0204090 LED Packaging Structure
A light emitting diode (LED) packaging structure including a metal pad, an electric static discharge (ESD) protection element and an LED chip is provided. The...
2016/0204089 PACKAGE WITH LOW STRESS REGION FOR AN ELECTRONIC COMPONENT
A device package includes a substrate having an active surface. Electrical connection bumps are deposited on the active surface and are arranged in an array...
2016/0204088 THREE DIMENSIONAL INTEGRATED CIRCUIT
A method comprises providing a first substrate having dielectric structures and conductive structures. Ions are implanted into the first substrate, the ions...
2016/0204087 LIGHT-EMITTING ASSEMBLIES COMPRISING AN ARRAY OF LIGHT-EMITTING DIODES HAVING AN OPTIMIZED LENS CONFIGURATION
Light emitting assemblies comprise a plurality of Light Emitting Diode (LED) dies arranged and attached to common substrate to form an LED array having a...
2016/0204086 METHODS OF MANUFACTURING WIDE BAND GAP SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE, AND WIDE BAND GAP...
A method of manufacturing a wide band gap semiconductor device includes the steps of preparing a wide band gap semiconductor substrate, separating the wide...
2016/0204085 SEMICONDUCTOR SYSTEM, DEVICE AND STRUCTURE
An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal...
2016/0204084 FRONT-TO-BACK BONDING WITH THROUGH-SUBSTRATE VIA (TSV)
Methods for forming a semiconductor device structure are provided. The method includes providing a first semiconductor wafer and a second semiconductor wafer....
2016/0204083 Integrated Semiconductor Device And Wafer Level Method Of Fabricating The Same
The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad...
2016/0204082 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large...
2016/0204081 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
The present invention provides a semiconductor device with an improved yield ratio and reduced height and manufacturing cost; and a method of manufacturing the...
2016/0204080 SEMICONDUCTOR PACKAGES AND METHODS FOR FABRICATING THE SAME
A semiconductor package comprising: a semiconductor chip; a connection pillar that is disposed adjacent to the semiconductor chip; a first heat dissipation...
2016/0204079 Methods and Apparatus of Packaging with Interposers
Methods and apparatus for forming a semiconductor device package on an interposer using a micro-bump layer are disclosed. The micro-bump layer may comprise...
2016/0204078 BONDING PROCESS USING TEMPERATURE CONTROLLED CURVATURE CHANGE
A first substrate including a radius of curvature and a stressor layer is first provided. An outermost bowed, e.g., curved, surface of the first substrate is...
2016/0204077 METHOD FOR MANUFACTURING ELECTRONIC DEVICE BY USING FLIP-CHIP BONDING
An electronic device is manufactured by providing a substrate on which a pad including an organic solderability preservative (OSP) film is formed, mounting a...
2016/0204076 Integrated Circuit Structure Having Dies with Connectors
An embodiment is an integrated circuit structure including a first die having a bump structure, and a second die having a pad structure. The first die is...
2016/0204075 Semiconductor chip and method of processing a semiconductor chip
Various embodiments provide a semiconductor chip, wherein the semiconductor chip comprises a first contact area and a second contact area both formed at a...
2016/0204074 DICING METHOD FOR POWER TRANSISTORS
Some embodiments relate to a method of dicing a semiconductor wafer. The semiconductor wafer that includes a device structure that is formed within a device...
2016/0204073 Semiconductor Package and Method of Manufacturing the Same
A semiconductor package includes a semiconductor chip mounted on a substrate, an insulating layer covering at least a portion of the semiconductor chip and...
2016/0204072 SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD FOR SAME
According to the embodiments, a semiconductor device includes a substrate, a plurality of insulating layers, a lower shield plate, a semiconductor device, an...
2016/0204071 SEMICONDUCTOR DIE AND DIE CUTTING METHOD
The present disclosure provides die cutting methods and semiconductor dies. A semiconductor substrate has a test region, isolation regions, and core regions. A...
2016/0204070 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A method for manufacturing a semiconductor device is provided. The method comprises the steps of: providing a transparent substrate having a visible region and...
2016/0204069 SEMICONDUCTOR DEVICE WITH REDUCED VIA RESISTANCE
A semiconductor interconnect structure that has a first portion included in an upper interconnect level and a second portion included in a lower interconnect...
2016/0204068 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A method includes forming a multilayered film including a conductive layer mainly containing aluminum, and a barrier metal layer formed thereon, forming a hard...
2016/0204067 ELECTRONIC PACKAGE AND METHOD OF CONNECTING A FIRST DIE TO A SECOND DIE TO FORM AN ELECTRONIC PACKAGE
Some embodiments relate to an electronic package. The electronic package includes a substrate that includes a plurality of buildup layers. A first die is...
2016/0204066 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
The present disclosure provides a semiconductor device and fabrication method thereof. A dielectric layer is formed on a first surface of a semiconductor...
2016/0204065 INTEGRATED CIRCUITS WITH ELECTRONIC FUSE STRUCTURES
Integrated circuits including electronic fuse structures are disclosed. In some examples, the electronic fuse structure includes a fuse part and first and...
2016/0204064 SIZE-FILTERED MULTIMETAL STRUCTURES
A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in...
2016/0204063 DIELECTRIC THIN FILM ELEMENT, ANTIFUSE ELEMENT, AND METHOD OF PRODUCING DIELECTRIC THIN FILM ELEMENT
A dielectric thin film element having a high humidity resistance is provided. A dielectric thin film element includes a capacitance section having a dielectric...
2016/0204062 TANK CIRCUIT STRUCTURE AND METHOD OF MAKING THE SAME
A tank circuit structure includes a first gate layer, a first substrate, a first shielding layer, a first conductive line and a first inter metal dielectric...
2016/0204061 CHIP PACKAGE AND FABRICATION METHOD THEREOF
A chip package including a chip, a first though hole, a conductive structure, a first isolation layer, a second though hole and a first conductive layer. The...
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