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Patent # Description
2016/0204060 SELF-ALIGNED REPAIRING PROCESS FOR BARRIER LAYER
A self-aligned repairing process for a barrier layer is provided. A repair layer is formed by chemical vapor deposition using an organometallic compound as a...
2016/0204059 Conductive Lines with Protective Sidewalls
Trenches are formed partially through a sacrificial layer at locations where bit lines are to be formed with some sacrificial material overlying vias. The...
2016/0204058 SEMICONDUCTOR DEVICE
A power supply wiring structure of a semiconductor device including a semiconductor chip flip-chip mounted on a substrate decreases the characteristic...
2016/0204057 SEMICONDUCTOR DEVICE
A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin...
2016/0204056 WIRING BOARD WITH INTERPOSER AND DUAL WIRING STRUCTURES INTEGRATED TOGETHER AND METHOD OF MAKING THE SAME
A wiring board with integrated interposer and dual wiring structures is characterized in that an interposer and a first wiring structure are positioned within...
2016/0204055 IC PACKAGE
An IC package having a semiconductor body that includes a monolithically integrated circuit and at least two metallic contact surfaces. The integrated circuit...
2016/0204054 PACKAGE CARRIER AND MANUFACTURING METHOD THEREOF
A manufacturing method of a package carrier is provided. A carrier having a connecting surface is provided. A releasable solder resist layer is formed on the...
2016/0204053 SEMICONDUCTOR PACKAGE
The invention provides a semiconductor package. The semiconductor package includes a lead frame including a die peddle. A supporting bar connects to the die...
2016/0204052 PACKAGED SEMICONDUCTOR DEVICE HAVING LEADFRAME FEATURES PREVENTING DELAMINATION
A semiconductor device has a leadframe with a first (401a) and a parallel second surface, and an assembly pad (410) bordered by two opposing sides, which...
2016/0204051 FLEXIBLE MICROSYSTEM STRUCTURE
A flexible microsystem structure is provided. The flexible microsystem structure includes a flexible substrate; and a chip disposed over the flexible...
2016/0204050 SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE
A method for manufacturing a semiconductor device may include the following steps: preparing a first substrate; providing a first conductor, which is...
2016/0204049 BRIDGE INTERCONNECT WITH AIR GAP IN PACKAGE ASSEMBLY
Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package...
2016/0204048 INTEGRATED CIRCUIT HEAT DISSIPATION USING NANOSTRUCTURES
An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature...
2016/0204047 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes: a semiconductor element having a solder region and a non-solder region on a first face; a first metal member disposed on the...
2016/0204046 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor chip, a resin mold portion sealing a component in which the semiconductor chip is included, and a bonding layer...
2016/0204045 3D TAP & SCAN PORT ARCHITECTURES
This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly...
2016/0204044 PROCESSING METHODS AND APPARATUS WITH TEMPERATURE DISTRIBUTION CONTROL
Wafer treatment process and apparatus is provided with a wafer carrier arranged to hold wafers and to inject a fill gas into gaps between the wafers and the...
2016/0204043 Methods for Monitoring Semiconductor Fabrication Processes Using Polarized Light
The inventive concept provides apparatuses and methods for monitoring semiconductor fabrication processes in real time using polarized light. In some...
2016/0204042 METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE
A method includes followings operations. A substrate including a first surface and a second surface is provided. The substrate and a transparent film are...
2016/0204041 METHOD OF INSPECTING SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME
A method of inspecting a semiconductor device includes providing a substrate, on which a mold layer with a plurality of mold openings is provided, milling the...
2016/0204040 MANUFACTURING APPARATUS OF SEMICONDUCTOR DEVICE AND MANAGEMENT METHOD OF MANUFACTURING APPARATUS OF...
According to one embodiment, a management method of a manufacturing apparatus of a semiconductor device, the method includes measuring a weight of a...
2016/0204039 TEMPERATURE-CONTROLLED IMPLANTING OF A DIFFUSION-SUPPRESSING DOPANT IN A SEMICONDUCTOR STRUCTURE
Semiconductor structures and methods of fabrication are provided for, for instance, inhibiting diffusion of active dopant within a semiconductor material. A...
2016/0204038 METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH IMPROVED IMPLANTATION PROCESSES
Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure...
2016/0204037 INTEGRATING VLSI-COMPATIBLE FIN STRUCTURES WITH SELECTIVE EPITAXIAL GROWTH AND FABRICATING DEVICES THEREON
Different n- and p-types of device fins are formed by epitaxially growing first epitaxial regions of a first type material from a substrate surface at a bottom...
2016/0204036 MAKING A DEFECT FREE FIN BASED DEVICE IN LATERAL EPITAXY OVERGROWTH REGION
Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls...
2016/0204035 BACKSIDE PROCESSED SEMICONDUCTOR DEVICE
A method of forming a semiconductor device includes: providing a first substrate, forming at least one transistor on a first surface of the first substrate;...
2016/0204034 METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A PLURALITY OF FINS AND AN ALIGNMENT/OVERLAY MARK
A method includes providing a semiconductor structure including a substrate that includes a material to be patterned. First and second mandrels are formed over...
2016/0204033 METHOD FOR SEPARATING SUBSTRATES AND SEMICONDUCTOR CHIP
Disclosed is a method for separating a substrate (1) along a separation pattern (4), in which method a substrate (1) is provided and an auxiliary layer (3) is...
2016/0204032 METHOD FOR DIVIDING A COMPOSITE INTO SEMICONDUCTOR CHIPS, AND SEMICONDUCTOR CHIP
The invention relates to a method for dividing a composite into a plurality of semiconductor chips along a dividing pattern. A composite, which comprises a...
2016/0204031 SHIELDED COPLANAR LINE
In one embodiment there is disclosed a method for manufacturing an integrated circuit in a semiconductor substrate including through vias and a coplanar line,...
2016/0204030 METHODS OF FORMING SEMICONDUCTOR DEVICE
A sacrificial layer is formed to cover the gate structures. The sacrificial layer is patterned to form a first opening in the sacrificial layer. A preliminary...
2016/0204029 LAMINATE AND CORE SHELL FORMATION OF SILICIDE NANOWIRE
Methods and apparatus for forming a metal silicide as nanowires for back-end interconnection structures for semiconductor applications are provided. In one...
2016/0204028 SUBSTRATE INCLUDING SELECTIVELY FORMED BARRIER LAYER
A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of...
2016/0204027 DIRECT DEPOSITION OF NICKEL SILICIDE NANOWIRE
Methods for direct deposition of a metal silicide nanowire for back-end interconnection structures for semiconductor applications are provided. In one...
2016/0204026 Contact Etch Stop Layers of a Field Effect Transistor
A representative method for fabricating a field effect transistor comprises forming a source region and a drain region disposed in a substrate; forming a gate...
2016/0204025 TRANSISTOR, SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device including a central region, side regions located in both sides of the central region, and conductive layers including a first barrier...
2016/0204024 METHOD FOR MANUFACTURING BONDED WAFER
Method for manufacturing a bonded wafer, including implanting at least one gas ion into a bond wafer from a bond wafer surface forming an ion implantation...
2016/0204023 MANUFACTURING METHOD FOR SEMICONDUCTOR SUBSTRATE
A technique disclosed herein relates to a manufacturing method for a semiconductor substrate having the bonded interface with high bonding strength without...
2016/0204022 SEMICONDUCTOR DEVICE STRUCTURES WITH IMPROVED PLANARIZATION UNIFORMITY, AND RELATED METHODS
Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a...
2016/0204021 SUPPORT STAGE FOR VACUUM APPARATUS
Apparatus for supporting a substrate (11) in respect of a vacuum system comprising a vacuum chamber, a cooling system (12), and a cradle (6) for supporting a...
2016/0204020 Bond Chuck, Methods of Bonding, and Tool Including Bond Chuck
A bonding chuck is discussed with methods of using the bonding chuck and tools including the bonding chuck. A method includes loading a first wafer on first...
2016/0204019 SUBSTRATE TRANSFER MECHANISMS
In one embodiment, a substrate support assembly includes a susceptor for supporting a substrate, and a supporting transfer mechanism coupled to the susceptor,...
2016/0204018 CONVEYING APPARATUS
A conveying apparatus includes a holding plate having a holding surface destined to face a surface of a wafer to be held; a restriction member on one end side...
2016/0204017 Embrittlement device, pick-up system and method of picking up chips
Various embodiments provide a method of picking up a chip from a carrier system, wherein the method comprises providing a carrier system comprising a plurality...
2016/0204016 WAFER PROCESSING METHOD
A wafer processing method which includes a protective tape attaching step of attaching a protective tape through an adhesive layer to a front side of a wafer...
2016/0204015 LOW TEMPERATURE ADHESIVE RESINS FOR WAFER BONDING
A method for adhesive bonding in microelectronic device processing is provided that includes bonding a handling wafer to a front side of a device wafer with an...
2016/0204014 BONDING METHOD INCLUDING ADJUSTING SURFACE CONTOURS OF A BONDING SYSTEM
A method of wafer bonding includes bonding a wafer to a carrier in a bonding system. The method further includes measuring thickness profile of the bonded...
2016/0204013 ADAPTABLE CASETTE HOLDER
An adaptable cassette holder that may include an interface; an interface holder for holding the interface; multiple recesses formed in the interface; multiple...
2016/0204012 SUBSTRATE CONTAINMENT WITH ENHANCED SOLID GETTER
A containment for one or more substrates has an enclosure that defines a contained volumetric area and included therein is a block or plate getter unit that...
2016/0204011 SUBSTRATE STORING CONTAINER
The lid body which includes a lid body main body having a lid body inner face and a lid body outer face, is detachable to the opening rim portion, and can...
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