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Patent # Description
2016/0211375 FINFET WITH MULTILAYER FINS FOR MULTI-VALUE LOGIC (MVL) APPLICATIONS AND METHOD OF FORMING
A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a...
2016/0211374 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor device includes: a sidewall insulating film; a gate electrode; source and drain regions; a first stress film; and a second stress film.
2016/0211373 METHODS FOR PREVENTING OXIDATION DAMAGE DURING FINFET FABRICATION
Embodiments of the present invention provide improved methods for fabricating field effect transistors such as finFETs. Stressor regions are used to increase...
2016/0211372 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A method for manufacturing a semiconductor device includes forming a fin structure over a substrate. An isolation insulating layer is formed so that an upper...
2016/0211371 SEMICONDUCTOR DEVICE INCLUDING FIN STRUCTURES AND MANUFACTURING METHOD THEREOF
A semiconductor Fin FET device includes a fin structure disposed over a substrate. The fin structure includes a channel layer. The Fin FET device also includes...
2016/0211370 SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL STRUCTURE
A semiconductor device includes a source/drain region, a barrier layer, and an interlayer dielectric. The barrier layer surrounds the source/drain region. The...
2016/0211369 Vertical Non-Planar Semiconductor Device for System-on-Chip (SoC) Applications
Vertical non-planar semiconductor devices for system-on-chip (SoC) applications and methods of fabricating vertical non-planar semiconductor devices are...
2016/0211368 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first dielectric layer and a...
2016/0211367 Metal Oxide Semiconductor Devices and Fabrication Methods
A semiconductor device includes a first well that is disposed in a semiconductor substrate. The semiconductor device further includes a second well that is...
2016/0211366 LATERAL DOUBLE DIFFUSED MOS TRANSISTORS
A lateral double diffused MOS transistor including a substrate, a source region and a drain region disposed in the substrate, a first contact and a second...
2016/0211365 Superjunction with Surrounding Lightly Doped Drain Region
A semiconductor device has a substrate and a lightly doped drain (LDD) region formed in the substrate. A superjunction is formed in the LDD region.
2016/0211364 Trench Gated Power Device With Multiple Trench Width and its Fabrication Process
Power devices, and related process, where both gate and field plate trenches have multiple stepped widths, using self-aligned process steps.
2016/0211363 NONVOLATILE MEMORY DEVICES HAVING SINGLE-LAYERED GATES AND METHODS OF FABRICATING THE SAME
A nonvolatile memory device includes an active region extending in a first direction and including a source region and a drain region that are respectively...
2016/0211362 MOSFETs with Multiple Dislocation Planes
A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET). The Method includes performing an implantation to form a...
2016/0211361 SEMICONDUCTOR DEVICE
A semiconductor device in which current sensing accuracy is maintained while ruggedness of a current sensing region is improved. The semiconductor device...
2016/0211360 VERTICAL POWER TRANSISTOR DEVICE
A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift...
2016/0211359 Integrated Power Device
A semiconductor device that includes a plurality of isolated half-bridges formed in a common semiconductor die.
2016/0211358 SEMICONDUCTOR DEVICE
A semiconductor device includes a first semiconductor layer on a substrate, a second semiconductor layer on the first semiconductor layer, the second...
2016/0211357 SEMICONDUCTOR DEVICE
A semiconductor device includes a first semiconductor layer on a substrate, a second semiconductor layer comprising a nitride semiconductor doped with p-type...
2016/0211356 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
In some aspects of the invention, an n-type field-stop layer can have a total impurity of such an extent that a depletion layer spreading in response to an...
2016/0211355 SEMICONDUCTOR DEVICE
A semiconductor device of the present invention includes a semiconductor layer, a plurality of gate trenches formed in the semiconductor layer, a gate...
2016/0211354 SEMICONDUCTOR DEVICE
A shield electrode is formed above a floating p region in a semiconductor layer and connected to a gate electrode in a trench. The shield electrode is composed...
2016/0211353 METHOD OF MANUFACTURING OXIDE THIN FILM TRANSISTOR
There is provided a method of manufacturing an oxide thin film transistor (TFT). The method includes forming a gate electrode on a substrate, forming a gale...
2016/0211352 METHOD OF TRIMMING FIN STRUCTURE
A method of trimming a fin structure includes the following operations: (i) forming a fin structure on a substrate; (ii) epitaxially growing an epitaxy...
2016/0211351 APPARATUS AND METHOD FOR EPITAXIALLY GROWING SOURCES AND DRAINS OF A FINFET DEVICE
An apparatus and a method for epitaxially growing sources and drains of a FinFET device. The apparatus comprises: a primary chamber; a wafer-loading chamber; a...
2016/0211350 MANUFACTURING METHOD OF FLEXIBLE DISPLAY DEVICE
A method of manufacturing a flexible display device, the method including forming a sacrificial layer on a carrier substrate such that the sacrificial layer...
2016/0211349 SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate, a trench extending from a front surface toward a rear surface side of the semiconductor substrate,...
2016/0211348 TRENCH LATERAL DIFFUSION METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
A trench lateral diffusion metal oxide semiconductor (LDMOS) device, disposed on a substrate, comprising: a transistor and an LDMOS transistor. The transistor...
2016/0211347 Method for Semiconductor Device Fabrication
Provided is a method of forming a semiconductor device. The method includes providing a substrate; depositing a flowable dielectric material layer over the...
2016/0211346 Epitaxial Channel Transistors and Die With Diffusion Doped Channels
Semiconductor structures can be fabricated by implanting a screen layer into a substrate, with the screen layer formed at least in part from a low diffusion...
2016/0211345 BIPOLAR JUNCTION TRANSISTOR WITH MULTIPLE EMITTER FINGERS
Device structures for a bipolar junction transistor and methods of fabricating a device structure for a bipolar junction transistor. A first semiconductor...
2016/0211344 MODIFIED SELF-ALIGNED CONTACT PROCESS AND SEMICONDUCTOR DEVICE
A semiconductor device includes a transistor and a contact pad over a substrate. The transistor includes a high-k dielectric layer, a work function metal...
2016/0211343 IMPLANTATION FORMED METAL-INSULATOR-SEMICONDUCTOR (MIS) CONTACTS
A method of forming a metal-insulator-semiconductor (MIS) contact, a transistor including the MIS contact, and the MIS contact are described. The method...
2016/0211342 IMPLANTATION FORMED METAL-INSULATOR-SEMICONDUCTOR (MIS) CONTACTS
A method of forming a metal-insulator-semiconductor (MIS) contact, a transistor including the MIS contact, and the MIS contact are described. The method...
2016/0211341 Transistor with Diamond Gate
A field effect transistor having a diamond gate electrode and a process for forming the same. In some embodiments, the device is an AlGaN/GaN ...
2016/0211340 IMPLANTATION FORMED METAL-INSULATOR-SEMICONDUCTOR (MIS) CONTACTS
A method of forming a metal-insulator-semiconductor (MIS) contact, a transistor including the MIS contact, and the MIS contact are described. The method...
2016/0211339 METAL GATE AND MANUFACUTRING METHOD THEREOF
The present disclosure provides a semiconductor structure, including an active region with a first surface; an isolated region having a second surface,...
2016/0211338 Semiconductor Devices, FinFET Devices, and Manufacturing Methods Thereof
Semiconductor devices, fin field effect transistor (FinFET) devices, and methods of manufacturing semiconductor devices are disclosed. In some embodiments, a...
2016/0211337 III-Nitride Transistor with Solderable Front Metal
Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using...
2016/0211336 Semiconductor Device with a Semiconductor Body Containing Hydrogen-Related Donors
A semiconductor device includes a semiconductor body with parallel first and second surfaces and containing hydrogen-related donors. A concentration profile of...
2016/0211335 SEMICONDUCTOR DEVICE
A semiconductor device includes a first semiconductor layer on a substrate, a second semiconductor layer containing an n-type dopant, on the first...
2016/0211334 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A silicon carbide semiconductor device capable of decreasing an ON-state resistance and improving a breakdown voltage. The silicon carbide semiconductor device...
2016/0211333 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A SiC semiconductor device includes a SiC substrate, a gate insulating film formed on a surface of the SiC substrate and made of SiO.sub.2, and a gate...
2016/0211332 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A silicon carbide semiconductor device capable of achieving a high current gain with a simplified construction is provided. A silicon carbide layer includes a...
2016/0211331 Stress Relieving Semiconductor Layer
A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing...
2016/0211330 HIGH ELECTRON MOBILITY TRANSISTOR
A high electron mobility transistor is provided, which includes a substrate, a superlattice structure formed on the substrate, and a transistor epitaxial...
2016/0211329 METHOD OF FORMING AN ISOLATION STRUCTURE IN A WELL OF A SUBSTRATE
A method includes forming an isolation structure in a well of a substrate. A portion of the isolation structure protrudes from a top surface of the well. The...
2016/0211328 COMPLEMENTARY METAL-OXIDE SILICON HAVING SILICON AND SILICON GERMANIUM CHANNELS
A silicon germanium on insulator (SGOI) wafer having nFET and pFET regions is accessed, the SGOI wafer having a silicon germanium (SiGe) layer having a first...
2016/0211327 COMPLEMENTARY METAL-OXIDE SILICON HAVING SILICON AND SILICON GERMANIUM CHANNELS
A silicon germanium on insulator (SGOI) wafer having nFET and pFET regions is accessed, the SGOI wafer having a silicon germanium (SiGe) layer having a first...
2016/0211326 FINFET STRUCTURE AND METHOD FOR MANUFACTURING THEREOF
Present disclosure provides a FinFET structure, including a fin and a gate surrounding a first portion of the fin. A dopant concentration in the first portion...
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