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Patent # Description
2016/0211275 DISPLAY APPARATUS
Provided is a display apparatus capable of stably repairing a bright spot defect to be a black spot without decreasing an aperture ratio of an array substrate....
2016/0211274 ELECTRICAL CONNECTION STRUCTURE WITH VIA HOLE, ARRAY SUBSTRATE AND DISPLAY DEVICE
An electrical connection structure with a via hole, an array substrate and a display device are provided, and the electrical connection structure with the via...
2016/0211273 DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME
A display device and a method of manufacturing the same are disclosed. In one aspect, the display device includes a plurality of pixels, wherein each pixel...
2016/0211272 SEMICONDUCTOR STRUCTURE WITH CONCAVE BLOCKING DIELECTRIC SIDEWALL AND METHOD OF MAKING THEREOF BY ISOTROPICALLY...
A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A spacer...
2016/0211271 Non-Volatile Memory With Silicided Bit Line Contacts
An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in...
2016/0211270 CONVEX SHAPED THIN-FILM TRANSISTOR DEVICE HAVING ELONGATED CHANNEL OVER INSULATING LAYER
The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and...
2016/0211269 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a semiconductor device includes: forming an insulating film above a semiconductor substrate; forming a conductive film on the...
2016/0211268 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME
A semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first...
2016/0211267 SEMICONDUCTOR STORAGE DEVICE
Probability of malfunction of a semiconductor storage device is reduced. A shielding layer is provided between a memory cell array (e.g., a memory cell array...
2016/0211266 MEMORY DEVICE AND ELECTRONIC DEVICE
A memory device with excellent writing performance and excellent storing performance is provided. In the memory device, a first layer overlaps with a second...
2016/0211265 SINGLE SOURCE/DRAIN EPITAXY FOR CO-INTEGRATING nFET SEMICONDUCTOR FINS AND pFET SEMICONDUCTOR FINS
A plurality of gate structures are formed straddling nFET semiconductor fins and pFET semiconductor fins which extend upwards from a surface of a semiconductor...
2016/0211264 Inverters and Manufacturing Methods Thereof
Inverters and methods of manufacture thereof are disclosed. In some embodiments, an inverter includes a substrate and a first tunnel FET (TFET) disposed over...
2016/0211263 NON-SILICON DEVICE HETEROLAYERS ON PATTERNED SILICON SUBSTRATE FOR CMOS BY COMBINATION OF SELECTIVE AND...
A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one...
2016/0211262 ISOLATION WELL DOPING WITH SOLID-STATE DIFFUSION SOURCES FOR FINFET ARCHITECTURES
An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that...
2016/0211261 METHOD AND STRUCTURE FOR FINFET DEVICES
A semiconductor device and a method of forming the same are disclosed. The device comprises a semiconductor substrate comprised of a first semiconductor...
2016/0211260 Devices Formed from a Non-Polar Plane of a Crystalline Material and Method of Making the Same
Materials, methods, structures and device including the same can provide a semiconductor device such as an LED using an active region corresponding to a...
2016/0211259 Stacked Device and Associated Layout Structure
Stacked devices and circuits formed by stacked devices are described. In accordance with some embodiments, a semiconductor post extends vertically from a...
2016/0211258 Reverse-Conducting Gated-Base Bipolar-Conduction Devices and Methods with Reduced Risk of Warping
Reverse-conducting IGBTs where the collector side includes diode terminal regions, and the semiconductor material is much thicker through the diode terminal...
2016/0211257 SEMICONDUCTOR DEVICE
In an IGBT portion, a first gate electrode is provided in a first trench via a first gate insulating film. A thickness of a first gate insulating film lower...
2016/0211256 SEMICONDUCTOR DEVICE
A power element and a temperature sensing element are formed on the same semiconductor substrate, and one end of a PN junction of the temperature sensing...
2016/0211255 Semiconductor device and method of manufacturing same
A method of manufacturing a semiconductor device, comprising: providing a substrate; forming a first trough structure, which comprises at least a first...
2016/0211254 ELECTROSTATIC DISCHARGE PROTECTION DEVICES
An ESD protection device includes a substrate having an active fin extending in a first direction, a plurality of gate structures extending in a second...
2016/0211253 ELECTRO-STATIC DISCHARGE STRUCTURE, CIRCUIT INCLUDING THE SAME AND METHOD OF USING THE SAME
An electro-static discharge (ESD) structure includes an input pad, and a first switching device electrically connected to the input pad. The ESD structure...
2016/0211252 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor layer having an element formation region in which a semiconductor element is formed. An element isolation well...
2016/0211251 SEMICONDUCTOR DEVICE LAYOUT, MEMORY DEVICE LAYOUT, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A layout of a semiconductor device includes active area regions, gate electrodes crossing the plurality of active area regions, spacers along sides of the...
2016/0211250 SEMICONDUCTOR SUBSTRATE ARRANGEMENT, A SEMICONDUCTOR DEVICE, AND A METHOD FOR PROCESSING A SEMICONDUCTOR SUBSTRATE
According to various embodiments, a semiconductor substrate arrangement may be provided, wherein the semiconductor substrate arrangement may include: a...
2016/0211249 ELECTRONIC PART, ELECTRONIC DEVICE, AND MANUFACTURING METHOD
An electronic part includes: a substrate; a first electrode configured to extend through the substrate and have a first opening size; a second electrode...
2016/0211248 Hybrid Bonding with Uniform Pattern Density
A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the...
2016/0211247 METHOD OF MANUFACTURING A CIRCUIT DEVICE
In one form, a method of manufacturing a circuit device comprises providing a lead frame comprising a plurality of leads, each comprising an island portion, a...
2016/0211246 SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS
The manufacturing yield of a semiconductor device is improved. There is provided a semiconductor device of a cascode coupling system, which is equipped with a...
2016/0211245 DISPLAY COMPRISING ULTRA-SMALL LEDS AND METHOD FOR MANUFACTURING SAME
Provided are a display including a nano-scale LED and a method for manufacturing the same. In detail, nano-scale LED devices, each of which has a nano unit,...
2016/0211244 Multi-Chip Structure and Method of Forming Same
A device comprises a first chip and a second chip stacked together to form a multi-chip structure, wherein the multi-chip structure is embedded in an...
2016/0211243 LAMINATED CHIP AND LAMINATED CHIP MANUFACTURING METHOD
A laminated chip includes: a first chip; a first wiring layer formed on the first chip; a second chip; a second wiring layer formed on the second chip; and a...
2016/0211242 REDUCED VOLUME INTERCONNECT FOR THREE-DIMENSIONAL CHIP STACK
A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive...
2016/0211241 3D INTEGRATED CIRCUIT
A three-dimensional integrated circuit (3D-IC) architecture incorporates multiple layers, each layer including at least one die and at least one switch to...
2016/0211240 MANUFACTURING METHOD OF ULTRA-THIN SEMICONDUCTOR DEVICE PACKAGE ASSEMBLY
A manufacturing method of ultra-thin semiconductor device package structure is provided. Firstly, a wafer including a plurality of semiconductor devices is...
2016/0211239 Package Having Substrate With Embedded Metal Trace Overlapped by Landing Pad
An embodiment package includes a conductive pillar mounted on an integrated circuit chip, the conductive pillar having a stepper shape, a metal trace partially...
2016/0211238 THERMAL COMPRESSION BONDING PROCESS COOLING MANIFOLD
Embodiments of a thermal compression bonding (TCB) process cooling manifold, a TCB process system, and a method for TCB using the cooling manifold are...
2016/0211237 PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE
A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface...
2016/0211236 SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME
Semiconductor packages and methods of forming the same may be provided. According to the semiconductor package of the present inventive concepts, a bump...
2016/0211235 BUMP STRUCTURES, SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PACKAGE HAVING THE SAME
The present disclosure relates to bump structures and a semiconductor device and semiconductor device package having the same. The semiconductor device...
2016/0211234 INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF
A conductive interconnect structure includes a contact pad; a conductive body connected to the contact pad at a first end; and a conductive layer positioned on...
2016/0211233 CHIP MODULE AND METHOD FOR FORMING THE SAME
A chip module is provided. The chip module includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a signal pad region...
2016/0211232 DEVICE AND METHOD FOR GENERATING IDENTIFICATION KEY
Provided are a device and method for generating an identification key using process variation during a bipolar junction transistor (BJT) process. A BJT may be...
2016/0211231 DEVICE AND METHOD FOR GENERATING IDENTIFICATION KEY
Provided is a device for generating an identification key using a process variation during a manufacturing process of a conductive layer. The device for...
2016/0211230 CHIP COMPRISING A PHASE CHANGE MATERIAL BASED PROTECTING DEVICE AND A METHOD OF MANUFACTURING THE SAME
An electronic chip including an integrated circuit arranged a face of a substrate, and a protection device arranged partially facing the integrated circuit is...
2016/0211229 MULTI-LAYER CIRCUIT USING METAL LAYERS AS A MOISTURE DIFFUSION BARRIER FOR ELECTRICAL PERFORMANCE
A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and...
2016/0211228 THERMALLY CURABLE RESIN SHEET FOR SEALING SEMICONDUCTOR CHIP, AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE
The present invention provides a thermally curable resin sheet for sealing a semiconductor chip having excellent reliability and storability while being...
2016/0211227 Semiconductor Device Including a Protection Structure
A device includes a semiconductor chip including a dicing edge. The device further includes an active structure arranged in a semiconductor material of the...
2016/0211226 INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT
In various embodiments, an integrated circuit is provided. The integrated circuit may include a semiconductor chip and an electrically conductive composite...
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