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Patent # Description
2016/0210275 IDENTIFYING CHANGES FOR ONLINE DOCUMENTS
Techniques and systems are disclosed for providing changed content identification for an online document that is accessed by a user or user agent. A reference...
2016/0210274 Document Publishing Model
Some embodiments described herein provide a content publishing tool for publishing documents to a content distribution system. The content publishing tool in...
2016/0210273 IN-MEMORY WORKSPACE MANAGEMENT
In in-memory workspace management, a request is received from a user to open a document. It is determined whether the document is opened. Upon determining that...
2016/0210272 RICH TEXT HANDLING FOR A WEB APPLICATION
A method and apparatus for representing and controlling documents including rich text for Web based applications and browsers is provided so that editing of...
2016/0210271 INFORMATION PROCESSING TERMINAL AND INFORMATION PROCESSING METHOD
To provide an information processing terminal and information processing method capable of supplying a user with information useful for selecting link...
2016/0210270 SYSTEMS AND METHODS FOR ACCESSING AND STORING SNAPSHOTS OF A REMOTE APPLICATION IN A DOCUMENT
Computer-implemented systems and methods are disclosed to interface with a storage device storing a file, wherein the file comprises first data associated with...
2016/0210269 CONTENT DISPLAY SYNCHRONIZED FOR TRACKED E-READING PROGRESS
A method executed in a processor of a computing device for syncing content is provided. The method includes receiving a request for content syncing at a...
2016/0210268 METHODS AND SYSTEMS FOR MANAGING VISUAL TEXT OBJECTS USING AN OUTLINE-LIKE LAYOUT
We describe methods and systems for managing visual objects within an interactive visual interface controlled by a digital computation device. More...
2016/0210267 DEPLOYING MOBILE DEVICE DISPLAY SCREEN IN RELATION TO E-BOOK SIGNATURE
A method and system for deploying a display screen of an electronic personal display device. The device includes a processor, primary and secondary touch...
2016/0210266 METHOD FOR PREDICTING HYSTERESIS CURVE MODEL OF MAGNETORHEOLOGICAL SYSTEM
The present invention claims a method for predicting a hysteresis curve model of a magnetorheological system based on Equation 1: {umlaut over ...
2016/0210265 APPARATUS FOR CONTROLLING INVERSE FAST FOURIER TRANSFORM INPUT IN LONG TERM EVOLUTION SYSTEM
Disclosed is an apparatus for controlling an IFFT input in a LTE system. The apparatus includes: a first multiplexer configured to select a portion of data...
2016/0210264 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Disclosed is a semiconductor device including an insulating layer, a source electrode and a drain electrode embedded in the insulating layer, an oxide...
2016/0210263 SCHEDULING AND EXECUTION OF DAG-STRUCTURED COMPUTATION ON RDMA-CONNECTED CLUSTERS
A server and/or a client stores a metadata hash map that includes one or more entries associated with keys for data records stored in a cache on a server,...
2016/0210262 PORTABLE INSTRUMENT AND DOCKING STATION WITH DIVIDED UNIVERSAL SERIAL BUS COMMUNICATION DEVICE
A universal serial bus (USB) communication system includes a portable instrument and a docking station that communicate with a host device using a divided USB...
2016/0210261 METHOD AND APPARATUS TO MANAGE THE DIRECT INTERCONNECT SWITCH WIRING AND GROWTH IN COMPUTER NETWORKS
The present invention provides a method for managing the wiring and growth of a direct interconnect network implemented on a torus or higher radix interconnect...
2016/0210260 RESOURCE DOMAIN PARTIONING IN A DATA PROCESSING SYSTEM
A resource domain controller in a data processing system stores information that is used to group various resources, such as bus masters and peripherals, into...
2016/0210259 VIRTUAL PCI EXPANDER DEVICE
Methods, systems, and computer program products for notifying a virtual machine of an expander coupled to a first virtual root bus, probing the expander to...
2016/0210258 PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) HOSTS ADAPTED TO SUPPORT REMOTE PCIe ENDPOINTS
Aspects disclosed in the detailed description include peripheral component interconnect express (PCIe) hosts adapted to support remote PCIe endpoints. In this...
2016/0210257 COMMUNICATION CONTROLLER FOR ELECTRONIC DEVICES
A communication controller for an electronic device comprises a hub controller; an internal port for connecting to an I/O interface of the electronic device,...
2016/0210256 MOTHERBOARD AND ELECTRONIC DEVICE UTILIZING THE SAME
A motherboard applied in an electronic device includes a platform controller hub (PCH), a basic input and output system (BIOS), and a control circuit. The BIOS...
2016/0210255 INTER-PROCESSOR BUS LINK AND SWITCH CHIP FAILURE RECOVERY
A system is disclosed in which the system may include multiple bus switches, and multiple processors. Each processor may be coupled to each bus switch. Each...
2016/0210254 FAST LINK TRAINING IN EMBEDDED SYSTEMS
Fast link training in embedded systems is disclosed. In one aspect, a host takes advantage of situations in which the host is coupled to one or more static...
2016/0210253 Serial bus system with switching modules
A serial bus system with a plurality of bus modules (2'-4') connected thereto, wherein the data traffic can be administered on the serial bus (1) by means of...
2016/0210252 DMA CONTROL DEVICE, MICRO CONTROL UNIT, AND DMA CONTROL METHOD
A direct memory access (DMA) control device including: a basic-function setting register used to perform DMA operation; and a scatter-gather setting register...
2016/0210251 MEMORY CHANNEL THAT SUPPORTS NEAR MEMORY AND FAR MEMORY ACCESS
A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first...
2016/0210250 MOTHERBOARD WITH DUAL MEMORY SLOTS AND COMPUTER SYSTEM WITH THE SAME
A motherboard with dual memory slot is disclosed. The motherboard includes multiple first memory slots, multiple second memory slots, a storage unit, and a...
2016/0210249 BUS ACCESS CONTROLLER, HARDWARE ENGINE, CONTROLLER, AND MEMORY SYSTEM
According to one embodiment, there is provided a bus access controller including a memory, multiple buffers, and an issuance circuit. Information necessary for...
2016/0210248 INFORMATION PROCESSING SYSTEM, METHOD AND MEDIUM
An information processing system includes: a shared memory including a plurality of regions comprising first region and second region; a memory token storing...
2016/0210247 ACCESS KEY GENERATION FOR COMPUTER-READABLE MEMORY
In one example, a method includes receiving, by a controller device from a master device operably connected to the controller device, a memory access request...
2016/0210246 INSTRUCTION CACHE WITH ACCESS LOCKING
An instruction cache includes instruction storage, a plurality of lock indicators, and control logic. The instruction storage includes a plurality of cache...
2016/0210245 CIRCUIT FOR ACCESSING MEMORY AND ASSOCIATED ACCESSING METHOD
A circuit for accessing a memory is provided. The memory includes a scatter table storage region and a plurality of storage regions. The scatter table storage...
2016/0210244 IMPLEMENTING PAGING OPTIMIZATION TO AVOID POPULATE ON PAGE FAULT DURING AN IO READ
A method and system for implementing paging optimization to avoid populate on page fault during an Input Output (IO) read. A size of the IO read is evaluated....
2016/0210243 Memory Paging for Processors using Physical Addresses
A method and apparatus for memory paging is disclosed. A system includes a plurality of processor cores each configured to initiate requests to a memory by...
2016/0210242 VIRTUAL DISK ALIGNMENT ACCESS
Embodiments relate to a virtualized storage environment with one or more virtual machines operating on a host and sharing host resources. Each virtual machine...
2016/0210241 REDUCING A SIZE OF A LOGICAL TO PHYSICAL DATA ADDRESS TRANSLATION TABLE
A method may include forming, by a processor, a logical data address container comprising a plurality of logical data addresses. Each logical data address...
2016/0210240 VIRTUAL DISK ALIGNMENT ACCESS
Embodiments relate to a virtualized storage environment with one or more virtual machines operating on a host and sharing host resources. Each virtual machine...
2016/0210239 SYSTEM AND METHOD FOR IMPROVING A VICTIM CACHE MODE IN A PORTABLE COMPUTING DEVICE
Systems and methods for improved operation of a victim cache in a portable computing device (PCD) are presented. A lower level cache is operated as a victim to...
2016/0210238 UTILIZATION OF A DISTRIBUTED INDEX TO PROVIDE OBJECT MEMORY FABRIC COHERENCY
Embodiments of the invention provide systems and methods to implement an object memory fabric. Object memory modules may include object storage storing memory...
2016/0210237 STORAGE DEVICE, DATA ACCESS METHOD, AND PROGRAM RECORDING MEDIUM
Disclosed is a storage device which provides data with higher data throughput performance during in-memory storage access in an access environment with little...
2016/0210236 DYNAMIC DATA CACHES, DECODERS AND DECODING METHODS
Examples described include dynamic data caches (DDCs), decoders and decoding methods that may fit into a smaller width area. The DDCs, decoders and decoding...
2016/0210235 DATA PROCESSING SYSTEM HAVING COMBINED MEMORY BLOCK AND STACK PACKAGE
A data processing system includes a central processing unit (CPU), a control block configured to interface with the CPU, a cache memory configured to interface...
2016/0210234 MEMORY SYSTEM INCLUDING VIRTUAL CACHE AND MANAGEMENT METHOD THEREOF
Provided is a memory system including: a virtual cache configured to store cache data stored in an upper cache memory before power supply to the upper cache...
2016/0210233 Memory Descriptor List Caching and Pipeline Processing
Memory descriptor list caching and pipeline processing techniques are described. In one or more examples, a method is configured to increase efficiency of...
2016/0210232 CACHE COHERENCE PROTOCOL
The present disclosure relates to systems, methods, and computer program products for keeping multiple caches updated, or coherent, on multiple servers when...
2016/0210231 HETEROGENEOUS SYSTEM ARCHITECTURE FOR SHARED MEMORY
A processing unit includes one or more first cores. The one or more first cores and one or more second cores are part of a heterogeneous computing system and...
2016/0210230 SYSTEM AND METHOD FOR ADAPTIVE IMPLEMENTATION OF VICTIM CACHE MODE IN A PORTABLE COMPUTING DEVICE
Systems and methods for adaptive implementation of victim cache modes in a portable computing device (PCD) are presented. In operation, an upper level cache is...
2016/0210229 ACCELERATING CACHE STATE TRANSFER ON A DIRECTORY-BASED MULTICORE ARCHITECTURE
Technologies are generally described herein for accelerating a cache state transfer in a multicore processor. The multicore processor may include first,...
2016/0210228 ASYNCHRONOUS GARBAGE COLLECTION IN A DISTRIBUTED DATABASE SYSTEM
A method for asynchronous garbage collection in a distributed database is described herein, The method includes budding a set of candidates for garbage...
2016/0210227 METHOD AND SYSTEM FOR IDENTIFYING AREAS OF IMPROVEMENTS IN AN ENTERPRISE APPLICATION
The present disclosure relates to a method and a system for identifying areas of improvements in an enterprise application. In one embodiment, static and...
2016/0210226 METHOD AND APPARATUS FOR TESTING ELECTRONIC SYSTEM
A verification apparatus and method are disclosed for testing a device or system which is operable in a number of states through which it can transition in a...
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