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Patent # Description
2016/0217878 OPTOELECTRONIC NUCLEAR BATTERIES BASED ON RADIONUCLIDE NANOENCAPSULATION AND ORGANIC PHOTODIODES
Embodiments of the present disclosure relate to compositions including a doped material, batteries including the composition, photovoltaic devices including...
2016/0217877 SEALING BOLT AND SEALING SYSTEM
The present invention relates to a sealing bolt (2) for sealing a container lid (4) to a container body (6). The sealing bolt (2) comprises a seal stud (10)...
2016/0217876 FABRICATION OF METALLIC NUCLEAR FUEL
Systems and methods for fabricating metallic nuclear fuels are described. Methods may include preparing a metal feedstock charge; injection casting the metal...
2016/0217875 CONTAINMENT VESSEL DRAIN SYSTEM
A system for draining a containment vessel may include a drain inlet located in a lower portion of the containment vessel. The containment vessel may be at...
2016/0217874 Molten Salt Reactor
A molten salt reactor includes: a fluoride fuel salt; and a metal hydride moderator.
2016/0217873 POST PACKAGE REPAIR DEVICE
A post package repair (PPR) device is disclosed, which relates to a technology for masking a rupture operation in case of a post package repair (PPR)...
2016/0217872 ADAPTIVE ANALOG-TO-DIGITAL CONVERSION BASED ON SIGNAL PREDICTION
Methods and apparatuses are described for performing adaptive analog-to-digital conversion and time-to-delay conversion by using signal prediction to adjust...
2016/0217871 BIDIRECTIONAL SHIFT REGISTER AND IMAGE DISPLAY DEVICE USING THE SAME
A bidirectional shift register capable of performing a stable shift operation in both directions and an image display device using the same are provided. In...
2016/0217870 SHIFT REGISTER UNIT, GATE DRIVE CIRCUIT AND DISPLAY PANEL
Provided are a shift register unit, a gate drive circuit, and a display panel. The shift register unit includes a first to sixth transistor and a first and...
2016/0217869 Double lockout in non-volatile memory
A double lockout programming technique is provided having a hidden delay between programming and verification. A temporary lockout stage and a permanent...
2016/0217868 Pre-Program Detection Of Threshold Voltages Of Select Gate Transistors In A Memory Device
A memory device includes memory cells arranged in NAND strings between select gate transistors. A threshold voltage (Vth) distribution of the select gate...
2016/0217867 INFERRING THRESHOLD VOLTAGE DISTRIBUTIONS ASSOCIATED WITH MEMORY CELLS VIA INTERPOLATION
The present disclosure includes apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation. A number...
2016/0217866 SEMICONDUCTOR DEVICE BEING CAPABLE OF IMPROVING THE BREAKDOWN CHARACTERISTICS
A semiconductor device, wherein the semiconductor device includes a high-voltage supply circuit suitable for supplying a high voltage; a discharge circuit...
2016/0217865 Method Of Reducing Hot Electron Injection Type Of Read Disturb In Dummy Memory Cells
Read disturb is reduced for dummy memory cells in a charge-trapping memory device such as a 3D memory device. The memory device includes a selected NAND string...
2016/0217864 Non-volatile Split Gate Memory Device And A Method Of Operating Same
A non-volatile memory device that a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is in the semiconductor...
2016/0217863 SEMICONDUCTOR DEVICE
A semiconductor device includes a plurality of memory blocks including a plurality of memory cells, wherein the plurality of memory cells are divided into a...
2016/0217862 NON-VOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION
A non-volatile memory device receives a start command through a command line, receives an address through an address line, receives at least one setting value...
2016/0217861 Split Voltage Non-Volatile Latch Cell
A memory including an array of non-volatile latch (NVL) cells and method of operating the same are provided. In one embodiment, each NVL cell includes a...
2016/0217860 Partial Block Erase For Block Programming In Non-Volatile Memory
A non-volatile memory system utilizes partial block erasing during program operations to mitigate the effects of programming pass voltage disturbances. A...
2016/0217859 SEMICONDUCTOR DEVICE
A semiconductor device includes a memory block including memory cells coupled to word lines, and an operation circuit configured to perform a program loop on...
2016/0217858 Immediate Feedback Before or During Programming
A system and method of programming user data into a memory cell includes receiving a first user data to be programmed in a memory controller, selecting a...
2016/0217857 ADAPTIVE MULTI-PAGE PROGRAMMING METHODS AND APPARATUS FOR NON-VOLATILE MEMORY
A method is provided for programming a memory cell connected to a selected word line in a memory device. The method includes performing one programming pass of...
2016/0217856 METHOD AND CIRCUIT FOR SWITCHING A MEMRISTIVE DEVICE
A method of switching a memristive device applies a current ramp of a selected polarity to the memristive device. The resistance of the device during the...
2016/0217855 1-R RESISTIVE CHANGE ELEMENT ARRAYS USING RESISTIVE REFERENCE ELEMENTS
Methods for reading and programming one or more resistive change elements within a 1-R resistive change element array are disclosed. These methods include...
2016/0217854 APPARATUS AND METHODS FOR SENSING HARD BIT AND SOFT BITS
A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in...
2016/0217853 MULTISTAGE MEMORY CELL READ
A multistage read can dynamically change wordline capacitance as a function of threshold voltage of a memory cell being read. The multistage read can reduce...
2016/0217852 MEMORY OPERATING METHOD AND ASSOCIATED MEMORY DEVICE
A memory operating method comprises the following steps: a first read voltage is applied to the memory cell to read a first group of data levels of the memory...
2016/0217851 PROGRAMMING AND READING CIRCUIT FOR RESISTIVE RANDOM ACCESS MEMORY DEVICE
A resistive random access memory device includes: a first control line, a second control line, a RRAM cell, a first programmable current source and a first...
2016/0217850 METAL-INSULATOR PHASE TRANSITION FLIP-FLOP
A metal-insulator phase transition (MIT) flip-flop employs a selected one of a pair of bi-stable operating states to represent a logic state of the MIT...
2016/0217849 High Density Split-Gate Memory Cell
A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a...
2016/0217848 SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE
To provide a semiconductor device having a novel structure. To provide a semiconductor device excellent in reducing power consumption. A memory cell including...
2016/0217847 MEMORY SYSTEM INCLUDING PLURALITY OF DRAM DEVICES OPERATING SELECTIVELY
A memory system including a plurality of dynamic random access memory (DRAM) devices and a DRAM controller is provided. The plurality of DRAM devices includes...
2016/0217846 SEMICONDUCTOR DEVICES CONFIGURED TO GENERATE A BANK ACTIVE SIGNAL
A semiconductor device may include a refresh controller and a bank active signal generator. The refresh controller may be suitable for generating a level...
2016/0217845 INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD
An information processing apparatus includes a memory that is volatile, a memory controller connected to the memory in an information exchangeable manner, and...
2016/0217844 SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME
A semiconductor device includes an output controller and a data strobe signal generator. The output controller generates a period signal and a control clock...
2016/0217843 MEMORY REFRESH METHOD AND DEVICES
The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently...
2016/0217842 UNDERLAYERS FOR TEXTURED FILMS OF HEUSLER COMPOUNDS
A structure includes a tetragonal Heusler of the form Mn.sub.1+cX, in which X includes an element selected from the group consisting of Ge and Ga, with...
2016/0217841 RECONFIGURABLE SEMICONDUCTOR MEMORY APPARATUS AND OPERATING METHOD THEREOF
A reconfigurable semiconductor memory apparatus may include a memory cell array including a plurality of sub arrays. The reconfigurable semiconductor memory...
2016/0217840 Customizable Backup and Restore from NonVolatile Logic Array
Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from...
2016/0217839 HIGH CAPACITY MEMORY SYSTEM
The embodiments described herein describe technologies for memory systems. One implementation of a memory module includes multiple device sites coupled to the...
2016/0217838 SEMICONDUCTOR DEVICE
A semiconductor device may include an active controller configured to count pulses of an active signal, and activate an active masking signal for masking an...
2016/0217837 SEMICONDUCTOR DEVICE
A semiconductor device may include a first channel configured to output a first rising clock, a first falling clock, first rising data, and first falling data....
2016/0217836 SEMICONDUCTOR DEVICE
A semiconductor device includes a buffer block configured to generate a strobe signal by buffering an external strobe signal inputted through a first pad,...
2016/0217835 CIRCUITS FOR AND METHODS OF CONTROLLING THE OPERATION OF A HYBRID MEMORY SYSTEM
A circuit for controlling the operation of a memory system having different types of memory is described. The circuit comprises a first memory having a first...
2016/0217834 LOW VOLTAGE SENSING SCHEME HAVING REDUCED ACTIVE POWER DOWN STANDBY CURRENT
A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense...
2016/0217833 SENSE AMPLIFIER AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
A sense amplifier may include an amplifying section configured to amplify data of a segment line pair when an enable signal is activated and output amplified...
2016/0217832 DATA-DEPENDENT SELF-BIASED DIFFERENTIAL SENSE AMPLIFIER
A system and method of operating a twin-transistor single bit multi-time programmable memory cell to provide a high gain, sensing scheme for small signals. The...
2016/0217831 PROVIDING POWER AVAILABILITY INFORMATION TO MEMORY
The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a...
2016/0217830 METHOD FOR OPERATING SEMICONDUCTOR DEVICE
Provided is a highly reliable semiconductor device, a semiconductor device with a reduced circuit area, a memory element having favorable characteristics, a...
2016/0217829 SYSTEM AND METHOD FOR SYNCHRONIZATION OF SELECTABLY PRESENTABLE MEDIA STREAMS
A system for synchronizing audio and video of selectably presentable multimedia content includes a memory for storing a plurality of selectably presentable...
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