Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
2016/0225693 DIRECT BONDED COPPER SEMICONDUCTOR PACKAGES AND RELATED METHODS
A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC...
2016/0225692 SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF
A semiconductor device structure, for example a 3D structure, and a method for fabricating a semiconductor device. As non-limiting examples, various aspects of...
2016/0225691 SWAGED HEAT SINK AND HEAT SINK INTEGRATED POWER MODULE
A swaged heat includes a fin base having an outer periphery, and formed with a first fin insert groove and a second fin insert groove interposing a swage...
2016/0225690 SEMICONDUCTOR DEVICE
A semiconductor device includes: opposed first and second metal plates; a plurality of semiconductor elements each interposed between the first metal plate and...
2016/0225689 Apparatus and Semiconductor Structure including a Multilayer Package Substrate
An apparatus includes a multilayer package substrate having a plurality of layers. The apparatus also includes a first heat sink disposed over the package...
2016/0225688 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes a plurality of semiconductor elements; insulating circuit boards each including an insulating substrate, a circuit portion on a...
2016/0225687 PACKAGED ELECTRONIC DEVICE HAVING REDUCED PARASITIC EFFECTS AND METHOD
In one embodiment, an electronic package includes a substrate having a die pad plurality of lands embedded within substrate encapsulant. An electronic chip...
2016/0225686 Repackaged integrated circuit and assembly method
A packaged integrated circuit for operating reliably at elevated temperatures is provided. The packaged integrated circuit includes a reconditioned die, which...
2016/0225685 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
Provided are a semiconductor device including a terminal, a circuit substrate, and a case body and a method for manufacturing the semiconductor device. A...
2016/0225684 Semiconductor Package Structure and Manufacturing Method Thereof
A semiconductor package structure and manufacturing method thereof are provided, and the semiconductor package structure includes a semiconductor element, a...
2016/0225683 SUBSTRATE LIQUID PROCESSING APPARATUS, SUBSTRATE LIQUID PROCESSING METHOD, AND COMPUTER-READABLE STORAGE MEDIUM
Disclosed is a substrate liquid processing apparatus including a processing liquid storage unit that stores a processing liquid; a processing liquid supply...
2016/0225682 SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD AND STORAGE MEDIUM
Provided is a substrate processing apparatus, in which a processing liquid is supplied to a substrate W held horizontally by a substrate holding unit. A...
2016/0225681 PLASMA PROCESSING APPARATUS, PLASMA PROCESSING METHOD AND PLASMA PROCESSING ANALYSIS METHOD
A plasma processing apparatus, plasma processing method, and plasma processing analysis method in which a suitable combination of wavelength, time interval,...
2016/0225680 EXTRACTION OF RESISTANCE ASSOCIATED WITH LATERALLY DIFFUSED DOPANT PROFILES IN CMOS DEVICES
Various embodiments provide systems, computer program products and computer implemented methods. In some embodiments, a system includes a computer-implemented...
2016/0225679 DFT STRUCTURE FOR TSVS IN 3D ICS WHILE MAINTAINING FUNCTIONAL PURPOSE
Methods of testing TSVs using eFuse cells prior to and post bonding wafers in a 3D IC stack are provided. Embodiments include providing a wafer of a 3D IC...
2016/0225678 EMBEDDED SIGE EPITAXY TEST PAD
Techniques for measuring and testing a semiconductor wafer during semiconductor device fabrication include designating a test area on the top surface of the...
2016/0225677 METHODS OF FORMING FIN ISOLATION REGIONS ON FINFET SEMICONDUCTOR DEVICES USING AN OXIDATION-BLOCKING LAYER OF...
A method includes forming a plurality of trenches to define a fin, forming a first layer of insulating material in the trenches, forming a sidewall spacer on...
2016/0225676 METHODS OF FORMING FIN ISOLATION REGIONS UNDER TENSILE-STRAINED FINS ON FINFET SEMICONDUCTOR DEVICES
One illustrative method disclosed herein includes, among other things, forming a composite fin structure that is comprised of a first germanium-containing...
2016/0225675 METHOD OF MULTI-WF FOR MULTI-VT AND THIN SIDEWALL DEPOSITION BY IMPLANTATION FOR GATE-LAST PLANAR CMOS AND...
A method of forming RMG multi-WF layers for an nFET and pFET, and the resulting device are provided. Embodiments include forming a Si fin; forming a nFET RMG...
2016/0225674 METHODS OF FORMING NMOS AND PMOS FINFET DEVICES AND THE RESULTING PRODUCT
One illustrative method disclosed herein includes, among other things, recessing first and second fins to define replacement fin cavities in a layer of...
2016/0225673 HIGH MOBILITY TRANSISTORS
An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have...
2016/0225672 IMPLANT PROFILING WITH RESIST
A process for forming at least two different doping levels at the surface of a wafer using one photo resist pattern and implantation process step. A resist...
2016/0225671 Non-Planar I/O and Logic Semiconductor Devices having Different Workfunction on Common Substrate
Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic...
2016/0225670 PEELING APPARATUS, PEELING SYSTEM, AND PEELING METHOD
Provided is a peeling apparatus configured to suppress damage to a substrate, by forming a peeling start point. The peeling apparatus separates a superimposed...
2016/0225669 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
A method of fabricating a semiconductor package is disclosed. The method includes disposing semiconductor chips on a support substrate, forming a protection...
2016/0225668 TSV Formation Processes Using TSV-Last Approach
A device includes a semiconductor substrate having a front surface and a back surface opposite the front surface. An insulation region extends from the front...
2016/0225667 SEMICONDUCTOR STRUCTURE HAVING SOURCE/DRAIN GOUGING IMMUNITY
There is set forth herein a method of fabricating a semiconductor structure, the method including forming a conductive metal layer over a source/drain region....
2016/0225666 FORMING MERGED LINES IN A METALLIZATION LAYER BY REPLACING SACRIFICIAL LINES WITH CONDUCTIVE LINES
A method includes forming a plurality of sacrificial lines embedded in a first dielectric layer. A line merge opening and a line cut opening are formed in a...
2016/0225665 INTERCONNECT WIRES INCLUDING RELATIVELY LOW RESISTIVITY CORES
A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes...
2016/0225664 Semiconductor Device and Fabricating Process for the Same
A semiconductor device and a fabricating process for the same are provided. The semiconductor device includes a base layer having a part of a reactive...
2016/0225663 SEMICONDUCTOR DEVICE HAVING STABLE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
The semiconductor device includes a stacked structure including conductive layers and insulating layers alternately stacked; semiconductor patterns configured...
2016/0225662 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon and an...
2016/0225661 METAL WIRING OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A metal wiring for applying a voltage to a semiconductor component of a semiconductor device, the semiconductor device comprising a low voltage applying region...
2016/0225660 FORMATION OF ISOLATION SURROUNDING WELL IMPLANTATION
Embodiments of present invention provide a method of making well isolations. The method includes forming a hard-mask layer on top of said substrate; forming a...
2016/0225659 METHODS OF FORMING FIN ISOLATION REGIONS ON FINFET SEMICONDUCTOR DEVICES BY IMPLANTATION OF AN...
One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, the fin having a lower first section that...
2016/0225658 SEMICONDUCTOR DEVICES INCLUDING SUPPORTING PATTERNS IN GAP REGIONS BETWEEN CONDUCTIVE PATTERNS AND METHODS OF...
An integrated circuit device includes spaced apart conductive patterns on a substrate surface, and a supporting pattern on the substrate surface between...
2016/0225657 LOCALIZED REGION OF ISOLATED SILICON OVER DIELECTRIC MESA
An integrated circuit is formed by forming an isolation mesa over a single crystal substrate which includes silicon, and forming a first epitaxial layer on the...
2016/0225656 WAFER PROCESSING SYSTEM WITH CHUCK ASSEMBLY MAINTENANCE MODULE
A wafer processing system has a ring maintenance module for loading wafers into a chuck assembly, and for cleaning and inspecting the chuck assembly used in...
2016/0225655 SUCTION STAGE, LAMINATION DEVICE, AND METHOD FOR MANUFACTURING LAMINATED SUBSTRATE
According to the embodiment, a suction stage includes a mounting section configured to mount a first substrate, and an evacuation section configured to...
2016/0225654 CARRIER TAPE AND PACK
A carrier tape is provided from which LEDs can be easily picked up. A carrier tape for accommodating an LED includes a sheet defining recessed embossed...
2016/0225653 METHOD OF PROVIDING A FLEXIBLE SEMICONDUCTOR DEVICE AND FLEXIBLE SEMICONDUCTOR DEVICE THEREOF
Some embodiments include a method. The method can include providing a carrier substrate having an edge. Further, the method can include providing a...
2016/0225652 LOW TEMPERATURE CHUCK FOR PLASMA PROCESSING SYSTEMS
A wafer chuck assembly includes a puck, a shaft and a base. The puck includes an electrically insulating material that defines a top surface of the puck; a...
2016/0225651 HIGH TEMPERATURE CHUCK FOR PLASMA PROCESSING SYSTEMS
A wafer chuck assembly includes a puck, a shaft and a base. An insulating material defines a top surface of the puck, a heater element is embedded within the...
2016/0225650 SUBSTRATE HOLDING DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
According to one embodiment, there is provided a substrate holding device, in which, when a substrate is mounted on a chuck main body, gas is exhausted from a...
2016/0225649 LOAD PORT AND METHOD FOR LOADING AND UNLOADING CASSETTE
A load port for a processing tool includes a carrier, a carrier actuator, an input table, an input table actuator, and a controller. The carrier has a...
2016/0225648 PURGING DEVICE AND PURGING METHOD
The safety of a worker is ensured, and the area in which purging is halted is limited to the minimum. The inner space of a device is divided into a working...
2016/0225647 SUBSTRATE STORAGE CONTAINER
A substrate storing container that stores substrates composed of semiconductor wafers includes: a locked portion that is arranged at a center portion of an...
2016/0225646 TRANSFER CHAMBERS WITH AN INCREASED NUMBER OF SIDES, SEMICONDUCTOR DEVICE MANUFACTURING PROCESSING TOOLS, AND...
A transfer chamber configured to be used during semiconductor device manufacturing is described. Transfer chamber includes at least one first side of a first...
2016/0225645 TEMPERATURE CONTROL MECHANISM, TEMPERATURE CONTROL METHOD AND SUBSTRATE PROCESSING APPARATUS
There is provided a temperature control mechanism comprising: a plurality of combinations of a heater and a thyristor, wherein at least one combination of the...
2016/0225644 SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD
A first holding plate and a second holding plate are provided. The first holding plate has a first flat plate portion facing a bottom surface of a substrate...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.