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Patent # Description
2016/0224493 UNIVERSAL SERIAL BUS (USB) KVM SWITCH USING VIRTUAL USB FOR SWITCHING AMONG MULTIPLE HOSTS
A Universal Serial Bus (USB) keyboard-video-mouse (KVM) switch for connection between at least one host and at least one USB device is disclosed. The USB KVM...
2016/0224492 APPARATUS, SYSTEM AND METHOD OF PROTOCOL ADAPTATION LAYER (PAL) COMMUNICATION TO INDICATE TRANSITIONING A...
Some demonstrative embodiments include apparatuses, systems and/or methods of transitioning a device to a default state. For example, an apparatus may include...
2016/0224491 METHOD AND DEVICE FOR IMPLEMENTING LTE BASEBAND RESOURCE POOL
A method for implementing a baseband resource pool in an LTE base station is provided. The LTE base station includes a main control module, a master board a...
2016/0224490 COMMAND QUEUE FOR COMMUNICATION BUS
Performing transactions on a bus by first generating a sequence of commands by an initiator module and queuing the sequence of commands in a queue module. A...
2016/0224489 VOLTAGE MODE AND CURRENT MODE DEVICE ENUMERATION
An enumeration technique is provided that includes a master/slave embodiment and a half-duplex embodiment.
2016/0224488 BIDIRECTIONAL COMMUNICATION METHOD BETWEEN A MASTER TERMINAL AND A SLAVE TERMINAL ON A SINGLE TRANSMISSION LINE
A bidirectional communication method between a master terminal and a slave terminal on a single transmission line includes the master terminal transmitting an...
2016/0224487 TAG ALLOCATION IN A PCIE APPLICATION LAYER
Embodiments herein provide for tag allocation in a PCIe application layer. In one embodiment, an apparatus operable to interface with a plurality of virtual...
2016/0224486 INTERRUPT-DRIVEN I/O ARBITER FOR A MICROCOMPUTER SYSTEM
An I/O (input/output) bus arbiter to be used in conjunction with a compatible CPU (processor) to effect burst mode data transfers in all I/O accesses that...
2016/0224485 PROCESSOR MODEL USING A SINGLE LARGE LINEAR REGISTERS, WITH NEW INTERFACING SIGNALS SUPPORTING FIFO-BASE I/O...
A processor or CPU architecture that implements many enabling technologies proven to enhance data through put supporting the synchronous burst data transfer....
2016/0224484 TRANSMITTING INTER-PROCESSOR INTERRUPT MESSAGES BY PRIVILEGED VIRTUAL MACHINE FUNCTIONS
Systems and methods for transmitting inter-processor interrupt messages by privileged virtual machine functions. An example method may comprise: mapping, by a...
2016/0224483 CONTROLLING OPERATIONS ACCORDING TO ANOTHER SYSTEM'S ARCHITECTURE
An I/O device operating according to a native computer architecture is accessed by a primary computer system operating according to a primary computer...
2016/0224482 INFORMATION PROCESSING APPARATUS AND COMPUTER-READABLE RECORDING MEDIUM HAVING PROGRAM RECORDED THEREIN
Processing performance of inter-virtual OS communication is improved by including a first storage processing unit that stores shared data in a data sharing...
2016/0224481 MULTIPROCESSOR CACHE BUFFER MANAGEMENT
In an approach for managing data transfer across a bus shared by processors, a request for a first set of data is received from a first processor. A request...
2016/0224480 SEMICONDUCTOR MEMORY APPARATUS AND DATA INPUT/OUTPUT METHOD THEREOF
A semiconductor memory apparatus may include a write data bus inversion unit and a write data polarity change unit. The write data bus inversion unit may...
2016/0224479 COMPUTER SYSTEM, AND COMPUTER SYSTEM CONTROL METHOD
The computer system includes a server, and a storage system having two controllers. The server is connected to the two controllers, and has a dispatch module...
2016/0224478 REGISTER DEVICE AND METHOD FOR SOFTWARE PROGRAMMING
A communication device is provided. The communication device includes a master interface unit that is configured to provide an interface between a processor...
2016/0224477 HOMOGENOUS DEVICE ACCESS METHOD WHICH REMOVES PHYSICAL DEVICE DRIVERS IN A COMPUTER OPERATING SYSTEM
A model and access method for devices to be homogenous irrespective whether they be character or block types. The access method is closely coupled between a...
2016/0224476 PROTECT INFORMATION STORED IN ECU FROM UNINTENTIONAL WRITING AND OVERWRITING
Systems and methods that facilitate protecting vehicle impact event data from overwrite include an electronic control unit (ECU) having a processor that...
2016/0224475 SOFTWARE CRYPTOPROCESSOR
Security of information--both code and data--stored in a computer's system memory is provided by an agent loaded into and at run time resident in a CPU cache....
2016/0224474 FINE GRAINED ADDRESS REMAPPING FOR VIRTUALIZATION
Address remapping technologies are described. A method can include receiving, at a paging device of a system memory, a first physical address of an...
2016/0224473 Matrix Ordering for Cache Efficiency in Performing Large Sparse Matrix Operations
Mechanisms are provided for performing a matrix operation. A processor of a data processing system is configured to perform cluster-based matrix reordering of...
2016/0224472 VARIABLE CACHING STRUCTURE FOR MANAGING PHYSICAL STORAGE
A method for managing a variable caching structure for managing storage for a processor. The method includes using a multi-way tag array to store a plurality...
2016/0224471 METHODS AND SYSTEMS FOR MANAGING SYNONYMS IN VIRTUALLY INDEXED PHYSICALLY TAGGED CACHES
Methods and systems for managing synonyms in VIPT caches are disclosed. A method includes tracking lines of a copied cache using a directory, examining a...
2016/0224470 SYNCHRONIZATION VARIABLE MONITORING DEVICE, PROCESSOR, AND SEMICONDUCTOR APPARATUS
According to an embodiment, a synchronization variable monitoring device includes: an address comparator configured to compare a received address included in...
2016/0224469 METHOD OF MANAGING CONSISTENCY OF CACHES
The present invention relates to a method of transmitting a message comprising an integrity check and a header, between two processing units via a shared...
2016/0224468 EFFICIENT COHERENCY RESPONSE MECHANISM
A plurality of processing units are interconnected by a coherency network in accordance with a directed spanning tree. Each processing unit that is a leaf of...
2016/0224467 HIERARCHICAL CACHE STRUCTURE AND HANDLING THEREOF
A hierarchical cache structure comprises at least one higher level cache comprising a unified cache array for data and instructions and at least two lower...
2016/0224466 MEMORY SYSTEM AND OPERATION METHOD THEREOF
A memory system may include a first memory device including a first input/output buffer, a second memory device including a second input/output buffer, and a...
2016/0224465 HYBRID PROCESSOR
A hybrid computer that comprises a sequential processor, a single instruction massively parallel (SIMD) processor, and shared memory module that is shared...
2016/0224464 Valid Data Compression On SSD
In an embodiment of the invention, a method comprises: obtaining a first data block with a lowest number of valid data from a block record; moving a first...
2016/0224463 OPERATIONS INTERLOCK UNDER DYNAMIC RELOCATION OF STORAGE
A multi-boundary address protection range is provided to prevent key operations from interfering with a data move performed by a dynamic memory relocation...
2016/0224462 DEVICES AND METHODS FOR GENERATING TEST CASES
Devices and methods are provided for generating test cases. For example, one or more test design models including test element information are created, the...
2016/0224461 INJECTED INSTRUMENTATION APPLICATION MONITORING AND MANAGEMENT
Techniques to instrument computer applications to receive run-time telemetry, and to perform analysis on collected telemetry are described. Telemetry...
2016/0224460 SOFTWARE-DEFINED NETWORK APPLICATION DEPLOYMENT
Software-defined network application deployment can include receiving a developed SDN application and deploying the SDN application into a remote testing lab...
2016/0224459 REAL-TIME PROCESSING OF DATA STREAMS RECEIVED FROM INSTRUMENTED SOFTWARE
An analysis system receives data streams generated by instances of instrumented software executing on external systems. The analysis system evaluates an...
2016/0224458 SEMANTIC STACK TRACE
The present disclosure provides methods and systems for instrumenting a "semantic stack trace" (SST), where semantic information and dependency relationships...
2016/0224457 Methods and Systems to Identify and Reproduce Concurrency Violations in Multi-Threaded Programs
Methods and systems to identify and reproduce concurrency violations in multi-threaded programs are disclosed. An example method disclosed herein comprises...
2016/0224456 METHOD FOR VERIFYING GENERATED SOFTWARE, AND VERIFYING DEVICE FOR CARRYING OUT SUCH A METHOD
The invention relates to a method for verifying generated software (1), in particular of a computer program, which software (1) is produced by means of a...
2016/0224455 METHOD OF VERIFYING A SET OF TESTS, STORAGE MEDIUM, AND APPARATUS
A verifying method includes: creating, for each of tests, combination in which information identifying the test, information identifying input data, and...
2016/0224454 METHOD OF TESTING SOFTWARE
A method of testing software uses a debugger and a breakpoint handler. The debugger inserts a breakpoint in a target application and enters at least one...
2016/0224453 MONITORING THE QUALITY OF SOFTWARE SYSTEMS
A machine may be configured to monitor the quality of software systems based on key performance indicators associated with versions of various units of code....
2016/0224452 VALIDATION OF MULTIPROCESSOR HARDWARE COMPONENT
A method, apparatus and computer program product to be employed by a hardware component under validation, wherein the hardware component having a plurality of...
2016/0224451 Multi-Domain Fuse Management
A fuse controller comprises: a fuse bay, a bus, an engine, and an interface. The fuse bay stores repair and setting information for a plurality of fuse domains...
2016/0224450 Memory Built-In Self Test System
A memory built-in self test ("BIST") system comprises: a controller; a single port memory engine coupled to one or more single port memories; and a non-single...
2016/0224449 METHOD OF PERFORMING SINGLE EVENT UPSET TESTING
A system for simulating an event includes a memory system, a parity generator/validator, and a fault injector. The fault injector is configured to inject bits...
2016/0224448 TEST GENERATION USING EXPECTED MODE OF THE TARGET HARDWARE DEVICE
A method, apparatus and product for test generation. The method comprises generating a first set of instructions for a hardware component, that are to be...
2016/0224447 RELIABILITY VERIFICATION APPARATUS AND STORAGE SYSTEM
A reliability verification apparatus includes a memory device and a processor. A transition model of a plurality of nodes is stored in the memory device. Each...
2016/0224446 STORAGE CONTROLLER, METHOD, AND STORAGE MEDIUM
A storage controller out of a plurality of storage controllers used in a storage system, each of the plurality of storage controllers being configured to...
2016/0224445 SIZING A WRITE CACHE BUFFER BASED ON EMERGENCY DATA SAVE PARAMETERS
Embodiments relate to saving data upon loss of power. An aspect includes sizing a write cache buffer based on parameters related to carrying out this emergency...
2016/0224444 DISTRIBUTED SYSTEM, SERVER COMPUTER, DISTRIBUTED MANAGEMENT SERVER, AND FAILURE PREVENTION METHOD
A distributed system according to an exemplary embodiment includes first and second servers capable of executing the same application, wherein when a failure...
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