Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
2016/0240549 Method For Manufacturing Semiconductor Device
According to one embodiment, a method for manufacturing a semiconductor device includes forming a first film on a multilayer body including two or more stacked...
2016/0240548 MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
A memory device comprises plural of silicon-containing layers, string select lines (SSLs), strings, bit lines, metal strapped word lines and plural sets of...
2016/0240547 SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor memory device includes first plate-like members, a first wiring, a second plate-like member, a second wiring,...
2016/0240546 Non-Volatile Storage Element With Suspended Charge Storage Region
Suspended charge storage regions are utilized for non-volatile storage to decrease parasitic interferences and increase charge retention in memory devices....
2016/0240545 Memory Cells
A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor...
2016/0240544 NON-VOLATILE MEMORY DEVICE
A non-volatile memory device includes: a floating gate having a plurality of fingers; a first coupling unit including an active control gate which overlaps...
2016/0240543 SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE
A semiconductor device manufacturing method includes: forming an element isolation insulating film in a semiconductor substrate; forming a first film on a...
2016/0240542 CHARGE TRAPPING NONVOLATILE MEMORY DEVICES, METHODS OF FABRICATING THE SAME, AND METHODS OF OPERATING THE SAME
A charge trapping nonvolatile memory device includes a source region and a drain region disposed in an upper portion of a substrate and spaced apart from each...
2016/0240541 Methods and Apparatus for SRAM Cell Structure
An SRAM cell structure. In one embodiment, a bit cell first level contacts formed at a first and a second CVdd node, a first and a second CVss node, at a bit...
2016/0240540 SEMICONDUCTOR STRUCTURE HAVING A CENTER DUMMY REGION
A semiconductor structure is provided, including a substrate, a plurality of first semiconductor devices, a plurality of second semiconductor devices, and a...
2016/0240539 METAL LAYERS FOR A THREE-PORT BIT CELL
An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to...
2016/0240538 SEMICONDUCTOR DEVICE HAVING BURIED GATE, METHOD OF FABRICATING THE SAME, AND MODULE AND SYSTEM HAVING THE SAME
A semiconductor device includes junction regions formed in upper portions of both sidewalls of a trench formed in a semiconductor substrate, a first gate...
2016/0240537 SEMICONDUCTOR DEVICE INCLUDING FIN STRUCTURES AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a Fin FET transistor. The Fin FET transistor includes a first fin structure extending in a first direction, a gate stack and a...
2016/0240536 STRUCTURE AND FORMATION METHOD OF FINFET DEVICE
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a...
2016/0240535 CMOS NFET AND PFET COMPARABLE SPACER WIDTH
Embodiments of the present disclosure provide a structure including: a p-type field effect transistor (pFET device) and an n-type field effect transistor (nFET...
2016/0240534 TECHNIQUES FOR IMPROVING GATE CONTROL OVER TRANSISTOR CHANNEL BY INCREASING EFFECTIVE GATE LENGTH
Techniques are disclosed for improving gate control over the channel of a transistor, by increasing the effective electrical gate length (L.sub.eff) through...
2016/0240533 VERTICAL CMOS STRUCTURE AND METHOD
A method for forming stacked, complementary transistors is disclosed. Selective deposition techniques are used to form a column having a lower portion that...
2016/0240532 GATE-ALL-AROUND SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating...
2016/0240531 FinFET Device and Method of Manufacturing Same
A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin...
2016/0240530 FINFET STRUCTURE AND METHOD OF FORMING SAME
A method of forming a semiconductor device includes providing a semiconductor substrate. The semiconductor substrate includes fins formed thereon and a...
2016/0240529 DIE INCLUDING A SCHOTTKY DIODE
According to an embodiment of the invention there may be provided a die that may include (a) a first region of a first type; (b) a first conductor that...
2016/0240528 IGBT WITH BUILT-IN DIODE AND MANUFACTURING METHOD THEREFOR
An insulated gate bipolar translator (IGBT) with a built-in diode and a manufacturing method thereof are provided. The IGBT comprises: a semiconductor...
2016/0240527 STACKED DEVICES
An apparatus includes a substrate and an interposer associated with the substrate. The apparatus further includes a first device disposed within the substrate...
2016/0240526 Apparatus and Methods for Modulating Current / Voltage Response Using Multiple Semi-Conductive Channel Regions...
Apparatuses and methods for modulating current/voltage response using multiple semi-conductive channel regions (SCR) produced from different integrated...
2016/0240525 SEMICONDUCTOR DEVICES AND ARRANGEMENTS FOR ELECTROSTATIC DISCHARGE PROTECTION
A semiconductor device and device arrangement including a plurality of semiconductor regions of different conductivity types and a plurality of gates which...
2016/0240524 ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE
An electrostatic discharge (ESD) protection device includes a semiconductor layer having a first doped region, a second doped region, and an intrinsic region...
2016/0240523 Method for Manufacturing Semiconductor Device, Sheet-Shaped Resin Composition, and Dicing Tape-Integrated...
Provided is a method for manufacturing a semiconductor device, which can manufacture a semiconductor device at a high yield ratio by suppressing dissolution of...
2016/0240522 LIGHT-EMITTING APPARATUS
A light-emitting apparatus package of the present invention includes (i) an electrically insulated ceramic substrate, (ii) a first concave section formed in...
2016/0240521 Circuit Device And Method For The Production Thereof
A circuit device has a base plate, a first substrate arranged on a first outer side of the base plate, a second substrate arranged on a second outer side...
2016/0240520 CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
A chip package includes a chip, a dielectric bonding layer, a carrier, and a redistribution layer. The chip has a substrate, a conductive pad, and a protection...
2016/0240519 LIGHT-EMITTING DEVICE
A light-emitting device, having an overall color temperature when emitting light, includes a carrier, a first LED unit, and a second LED unit. The carrier has...
2016/0240518 LIGHT EMITTING DEVICE
Each of a plurality of light emitting elements has a polygonal shape with five or more corners. An interior angle at each of the corners is less than...
2016/0240517 DISPLAY DEVICE USING SEMICONDUCTOR LIGHT EMITTING DEVICES
A display device including a wiring substrate having a wiring electrode; a plurality of semiconductor light emitting devices which form pixels; and a...
2016/0240516 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE ARRAY
Present disclosure provides a method for manufacturing a semiconductor device array, including (1) providing a temporary substrate; (2) forming a plurality of...
2016/0240515 SIGNAL DELIVERY IN STACKED DEVICE
Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a...
2016/0240514 PACKAGE STRUCTURE AND ITS FABRICATION METHOD
This disclosure provides a package structure and its fabrication method. The package structure includes: a protective insulation layer; a wiring layer...
2016/0240513 PLANARITY-TOLERANT REWORKABLE INTERCONNECT WITH INTEGRATED TESTING
A structure includes an electrical interconnection between a first substrate including a plurality of protrusions and a second substrate including a plurality...
2016/0240512 MULTICHIP STACKING PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
The present invention relates to a multichip stacking package structure and a method for manufacturing the same, wherein the multichip stacking package...
2016/0240511 POWER PACKAGE LID
The present disclosure relates to a ring-frame power package. In this regard, the ring-frame power package includes a thermal carrier and a ring structure. The...
2016/0240510 MULTI-FUNCTION MINIATURIZED SURFACE-MOUNT DEVICE AND PROCESS FOR PRODUCING THE SAME
A surface-mount device (SMD) uses no conventional lead frame and contains a multi-function die module formed from either a single die or two or more dies...
2016/0240509 SEMICONDUCTOR PACKAGES
Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to...
2016/0240508 Package Structures and Methods of Forming the Same
Packages structure and methods of forming them are discussed. A structure includes a first die, a first encapsulant at least laterally encapsulating the first...
2016/0240507 WAFER-LEVEL PACKAGE WITH AT LEAST ONE INPUT/OUTPUT PORT CONNECTED TO AT LEAST ONE MANAGEMENT BUS
A wafer-level package has a first input/output (I/O) port, a second I/O port, a first semiconductor die, and a second semiconductor die. The first I/O port and...
2016/0240506 SOLDER ATTACH APPARATUS AND METHOD
An electronic device including a solder structure and methods of forming an electrical interconnection are shown. Solder structures are shown including a...
2016/0240505 METAL JOINING STRUCTURE USING METAL NANOPARTICLES AND METAL JOINING METHOD AND METAL JOINING MATERIAL
The present invention can give a joining structure using metal nanoparticles to join the same types or different types of metal where when one surface metal is...
2016/0240504 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A method for manufacturing a semiconductor device includes a first step of forming a first electrode on one main surface side of a semiconductor wafer; a...
2016/0240503 BONDING STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHODOF MANUFACTURING THE SAME
The present disclosure relates to bonding structures useful in semiconductor packages and methods of manufacturing the same. In an embodiment, the bonding...
2016/0240502 INTEGRATED CIRCUIT PACKAGING SUBSTRATE, SEMICONDUCTOR PACKAGE, AND MANUFACTURING METHOD
An integrated circuit (IC) packaging substrate includes a main body, at least one first conductive line, at least one second conductive line, and at least one...
2016/0240501 REDUCED VOLUME INTERCONNECT FOR THREE-DIMENSIONAL CHIP STACK
A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive...
2016/0240500 PACKAGED SEMICONDUCTOR DEVICES
A packaged semiconductor device is provided, which includes a substrate comprising a contact pad; a passivation layer disposed on the substrate, where the...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.