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Patent # Description
2016/0240499 Semiconductor Device and Method of Manufacturing the Same
To improve the reliability of a semiconductor device. The semiconductor device includes a plurality of wiring layers formed on a semiconductor substrate, a pad...
2016/0240498 PACKAGING PROCESS OF ELECTRONIC COMPONENT
A packaging process of an electronic component includes the following steps. Firstly, a semi-package unit is provided. The semi-package unit includes a first...
2016/0240497 WAFER-LEVEL PACKAGE HAVING MULTIPLE DIES ARRANGED IN SIDE-BY-SIDE FASHION AND ASSOCIATED YIELD IMPROVEMENT METHOD
A wafer-level package includes a plurality of dies and a plurality of connection paths. The dies include at least a first die and a second die. The dies are...
2016/0240496 DEVICES AND METHODS RELATED TO ELECTROSTATIC DISCHARGE PROTECTION BENIGN TO RADIO-FREQUENCY OPERATION
Disclosed are systems, devices and methods for providing electrostatic discharge (ESD) protection for integrated circuits. In some implementations, first and...
2016/0240495 INTEGRATED ANTENNAS IN WAFER LEVEL PACKAGE
A semiconductor module comprises an integrated circuit device, the IC device embedded in a compound material, wherein the compound material at least partially...
2016/0240494 RF PACKAGE AND MANUFACTURING METHOD THEREOF
Disclosed is a method of improving performance and increasing a freedom degree of design of an interconnect structure in a radio frequency (RF) package. The RF...
2016/0240493 SEMICONDUCTOR DEVICE PACKAGES AND METHOD OF MAKING THE SAME
The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a semiconductor device, a plurality of...
2016/0240492 ANTENNA ON CERAMICS FOR A PACKAGED DIE
An antenna is described on ceramics that may be used for a packaged die. In one example, a package has a die, a ceramic substrate over the die, an antenna...
2016/0240491 RF PACKAGE WITH NON-GASEOUS DIELECTRIC MATERIAL
An RF package including: an RF circuit; a non-gaseous dielectric material coupled to the RF circuit, and having a thickness based on a magnetic field in the RF...
2016/0240490 METHOD FOR FABRICATING SEMICONDUCTOR DEVICES HAVING REINFORCING ELEMENTS
The present disclosure provides a method for fabricating semiconductor devices having reinforcing elements. The method includes steps of providing a first...
2016/0240489 NOISE CANCELLATION FOR A MAGNETICALLY COUPLED COMMUNICATION LINK UTILIZING A LEAD FRAME
An integrated circuit package includes an encapsulation and a lead frame with a portion of the lead frame disposed within the encapsulation. The lead frame...
2016/0240488 SEMICONDUCTOR DEVICE WITH AN ISOLATION STRUCTURE COUPLED TO A COVER OF THE SEMICONDUCTOR DEVICE
A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling are presented. The semiconductor device...
2016/0240487 SEMICONDUCTOR DEVICE
Signal transmission characteristics of a semiconductor device are improved. A plurality of wirings of a wiring substrate on which a semiconductor chip is...
2016/0240486 CHIP PACKAGE STRUCTURE HAVING A SHIELDED MOLDING COMPOUND
A chip package structure including a main substrate, a carrier substrate, at least a chip, a molding compound, a shielding layer and a plurality of connection...
2016/0240485 MIDDLE-OF-LINE INTEGRATION METHODS AND SEMICONDUCTOR DEVICES
An electronic device includes a middle-of-line (MOL) stack. The electronic device includes a top local interconnect layer and a contact coupling the top local...
2016/0240484 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SAME
To provide a semiconductor device having improved reliability by improving a coupling property between a semiconductor chip and a bonding wire. A...
2016/0240483 INTERCONNECT STRUCTURES AND METHODS OF FORMATION
Interconnect structures and methods of formation of such interconnect structures are provided herein. In some embodiments, a method of forming an interconnect...
2016/0240482 LAYER STRUCTURE INCLUDING DIFFUSION BARRIER LAYER AND METHOD OF MANUFACTURING THE SAME
Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first...
2016/0240481 INTERPOSER SUBSTRATE, SEMICONDUCTOR STRUCTURE AND FABRICATING PROCESS THEREOF
Described herein are interposer substrate designs for warpage control, semiconductor structures including said interposer substrates, and fabricating processes...
2016/0240480 METAL OXIDE LAYERED STRUCTURE AND METHODS OF FORMING THE SAME
Some embodiment structures and methods are described. A structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a...
2016/0240479 SYSTEM AND METHOD FOR IDENTIFYING OPERATING TEMPERATURES AND MODIFYING OF INTEGRATED CIRCUITS
Aspects of the present disclosure include a computer-implemented method for identifying an operating temperature of an integrated circuit (IC), the method...
2016/0240478 MODIFIED TUNGSTEN SILICON
A method for forming a precision resistor or an e-fuse structure where tungsten silicon is used. The tungsten silicon layer is modified by implanting nitrogen...
2016/0240477 SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF
A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes an interconnect which includes an interconnect metal...
2016/0240476 SELF-ALIGNED INTEGRATED LINE AND VIA STRUCTURE FOR A THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
At least one via level dielectric layer and at least one line level dielectric layer are sequentially formed over an array of device structures. Conductive...
2016/0240475 SEMICONDUCTOR DEVICES INCLUDING SEALING REGIONS AND DECOUPLING CAPACITOR REGIONS
Semiconductor devices may include an internal circuit, a sealing region surrounding the internal circuit, and a decoupling capacitor region in the sealing...
2016/0240474 METHOD, SYSTEM AND COMPUTER READABLE MEDIUM USING STITCHING FOR MASK ASSIGNMENT OF PATTERNS
A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns...
2016/0240473 WAFER WITH IMPROVED PLATING CURRENT DISTRIBUTION
A semiconductor wafer is provided including a plurality of dies, each of the plurality of dies including a plurality of semiconductor devices, a plurality of...
2016/0240472 SEMICONDUCTOR DEVICE, LAYOUT DESIGN AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
A semiconductor device includes a first interconnect structure. The first interconnect structure includes a first interconnect portion, a second interconnect...
2016/0240471 EMBEDDED PACKAGING FOR DEVICES AND SYSTEMS COMPRISING LATERAL GaN POWER TRANSISTORS
Embedded packaging for devices and systems comprising lateral GaN power transistors is disclosed. The packaging assembly is suitable for large area, high power...
2016/0240470 SEMICONDUCTOR MODULES AND METHODS OF FORMING THE SAME
Electronic modules, and methods of forming and operating modules, are described. The modules include a capacitor, a first switching device, and a second...
2016/0240469 SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MAKING THE SAME
The present disclosure relates to a semiconductor substrate, a semiconductor package structure, and methods for making the same. A method includes providing a...
2016/0240468 ANISOTROPIC CONDUCTIVE FILM
An anisotropic conductive film that is capable of suppressing the occurrence of short circuit during anisotropic conductive connection of electrical components...
2016/0240467 WIRING BOARD AND SEMICONDUCTOR PACKAGE
A wiring board includes a wiring layer including a surface on which a recess is formed and a metal layer formed on a bottom surface of the recess. A surface of...
2016/0240466 ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF
A method for fabricating an electronic package is provided, including the steps of: providing at least a packaging structure, wherein the packaging structure...
2016/0240465 Reducing Cracking by Adjusting Opening Size in Pop Packages
A package includes a device die, a molding material molding the device die therein, and a surface dielectric layer at a surface of the package. A corner...
2016/0240464 HYBRID CIRCUIT BOARD AND METHOD FOR MAKING THE SAME, AND SEMICONDUCTOR PACKAGE STRUCTURE
A hybrid circuit board includes an insulate molding layer having a first surface and a second surface which is opposite to the first surface, a solder mask...
2016/0240463 SUBSTRATE COMPRISING STACKS OF INTERCONNECTS, INTERCONNECT ON SOLDER RESIST LAYER AND INTERCONNECT ON SIDE...
An integrated circuit device that includes a package substrate and a die coupled to the package substrate. The package substrate includes at least one...
2016/0240462 SEMICONDUCTOR SUBSTRATE STRUCTURE, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate...
2016/0240461 Semiconductor Package with Multi-Section Conductive Carrier
In one implementation, a power semiconductor package includes a non-contiguous, multi-section conductive carrier. A control transistor with a control...
2016/0240460 SINGULATION METHOD FOR SEMICONDUCTOR PACKAGE WITH PLATING ON SIDE OF CONNECTORS
A method of singulating semiconductor packages, the method comprising: providing a plurality of semiconductor dies coupled to a single common leadframe,...
2016/0240459 PAD CONFIGURATIONS FOR AN ELECTRONIC PACKAGE ASSEMBLY
Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening,...
2016/0240458 PACKAGE
A package includes: a plurality of lead frames configured to extend inwardly from an outer circumferential portion of the package; a die pad region surrounded...
2016/0240457 INTEGRATED CIRCUIT PACKAGES WITH DUAL-SIDED STACKING STRUCTURE
An integrated circuit package may include a first integrated circuit die attached to a front surface of a second integrated circuit die. An intermediate layer...
2016/0240456 SEMICONDUCTOR DEVICE
A semiconductor device (10) includes a metallic base plate (22) provided with an upper surface (22a) and a lower surface (22b), a plurality of insulating...
2016/0240455 SYSTEMS, APPARATUS, AND METHODS FOR HEAT DISSIPATION
Some examples of the disclosure include a semiconductor package having a heat spreader, an outer perimeter portion attached to the bottom of the heat spreader...
2016/0240454 Semiconductor Structure Having Thermal Backside Core
A semiconductor structure includes a semiconductor substrate having a recess disposed beneath a semiconductor device. The semiconductor structure also includes...
2016/0240453 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
The method of manufacturing a semiconductor device includes receiving a substrate. The substrate comprises at least one chip region and at least one scribe...
2016/0240452 SEMICONDUCTOR PACKAGES WITH SUB-TERMINALS AND RELATED METHODS
A semiconductor device package includes a substrate having first and second opposing surfaces. A first surface of a die couples to the second surface of the...
2016/0240451 INTERCONNECT STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE INTERCONNECT STRUCTURE
A semiconductor package includes a carrier, at least and adhesive portion, a plurality of micro pins and a die. The carrier has a first surface and second...
2016/0240450 SEMICONDUCTOR DEVICE
A semiconductor device has a semiconductor element provided with a functional surface on which a functional circuit is formed and with a back surface facing in...
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