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Patent # Description
2016/0239449 MANAGING SINGLE-WIRE COMMUNICATIONS
Systems, methods, circuits and computer-readable mediums for managing single-wire communications. In one aspect, a method includes starting a transmission...
2016/0239448 ADAPTIVE SPEED SINGLE-WIRE COMMUNICATIONS
Systems, methods, circuits and computer-readable mediums for adaptive speed single-wire communications. In one aspect, a method includes receiving a sensing...
2016/0239447 DATA ACQUISITION SYSTEM, ELECTRONIC DEVICE, AND DATA ACQUISITION TERMINAL
A data acquisition system includes an electronic device and a data acquisition terminal. The electronic device includes a data storage section and a first...
2016/0239446 SUPPORTING FLOW CONTROL MECHANISM OF BUS BETWEEN SEMICONDUCTOR DIES ASSEMBLED IN WAFER-LEVEL PACKAGE
A semiconductor die assembled in a wafer-level package includes a communication interface and a bus master. The bus master is coupled to a communication bus...
2016/0239445 SYSTEM ON A CHIP COMPRISING AN I/O STEERING ENGINE
Embodiments of the technology can provide steering of one or more I/O resources to compute subsystems on a system-on chip (SoC). The SoC may include a first...
2016/0239444 WAFER-LEVEL PACKAGE HAVING ASYNCHRONOUS FIFO BUFFER USED TO DEAL WITH DATA TRANSFER BETWEEN DIFFERENT DIES AND...
A wafer-level package has a first die and a second die. The first die has a first clock source arranged to generate a first clock, a first sub-system arranged...
2016/0239443 DMA CONTROLLER
A direct memory access (DMA) controller issues a standby request a predetermined period of time before data transfer having a high priority starts and...
2016/0239442 SCHEDULING VOLATILE MEMORY MAINTENANCE EVENTS IN A MULTI-PROCESSOR SYSTEM
Systems, methods, and computer programs are disclosed for scheduling volatile memory maintenance events. One embodiment is a method comprising: a memory...
2016/0239441 SYSTEMS AND METHODS FOR PROVIDING KERNEL SCHEDULING OF VOLATILE MEMORY MAINTENANCE EVENTS
Systems, methods, and computer programs are disclosed for scheduling volatile memory maintenance events. One embodiment is a method comprising: a memory...
2016/0239440 METHODS AND SYSTEMS FOR ROUTING IN A STATE MACHINE
A device includes a routing buffer. The routing buffer includes a first port configured to receive a signal relating to an analysis of at least a portion of a...
2016/0239439 Shared Buffer Arbitration For Packet-Based Switching
Methods and apparatuses regarding shared buffer arbitration for packet-based switching are described. A data packet may be received by a packet buffer...
2016/0239438 Instruction and Logic for a Binary Translation Mechanism for Control-Flow Security
A processor includes a front end, an execution pipeline, and a binary translator. The front end includes logic to receive an instruction and to dispatch the...
2016/0239437 Servicing of Network Software Components of Nodes of a Cluster Storage System
Described herein are method and apparatus for servicing software components of nodes of a cluster storage system. During data-access sessions with clients,...
2016/0239436 DATA SECURITY SYSTEM
A data security system includes a first computer system including: a memory for containing data, and a processing unit connected to the memory for locking and...
2016/0239435 MEMORY TAMPER DETECTION
A method and system for detecting tampering of authenticated memory blocks that are accessible by an untrusted host processor. by (1) periodically...
2016/0239434 POSITION-BASED REPLACEMENT POLICY FOR ADDRESS SYNONYM MANAGEMENT IN SHARED CACHES
A computer-implemented method includes receiving a request to access a cache entry in a shared cache. The request references a synonym for the cache entry. A...
2016/0239433 PREDICTIVE CACHE REPLACEMENT
Systems and methods for predictive cache replacement policies are provided. In particular, some embodiments dynamically capture and predict access patterns of...
2016/0239432 APPLICATION-LAYER MANAGED MEMORY CACHE
In order to prevent data thrashing and the resulting performance degradation, a computer system may maintain an application-layer cache space to more...
2016/0239431 HIGH PERFORMANCE PERSISTENT MEMORY FOR REGION-CENTRIC CONSISTENT AND ATOMIC UPDATES
A processor includes a processing core to execute an application comprising instructions encoding a transaction with a persistent memory via a non-persistent...
2016/0239430 LOCAL ACCESS DMA WITH SHARED MEMORY POOL
A processing device receives a first request from a virtual machine to register a memory region to a hardware device. The processing device generates a first...
2016/0239429 METHOD AND APPARATUS FOR ACCESSING DATA STORED IN A STORAGE SYSTEM THAT INCLUDES BOTH A FINAL LEVEL OF CACHE...
A data access system including a storage device and a processor, which includes one or more levels of cache (LOC). In response to data required by the...
2016/0239428 PLACEMENT ENGINE FOR A BLOCK DEVICE
A system, method, and computer program product are provided for implementing a reliable placement engine for a block device. The method includes the steps of...
2016/0239427 SET SELECTION OF A SET-ASSOCIATIVE STORAGE CONTAINER
A computer-implemented method includes generating a vector that is a random number. Two or more residue functions are applied to the vector to produce a state...
2016/0239426 SET SELECTION OF A SET-ASSOCIATIVE STORAGE CONTAINER
A computer-implemented method includes generating a vector that is a random number. Two or more residue functions are applied to the vector to produce a state...
2016/0239425 HIERARCHICAL PRE-FETCH PIPELINING IN A HYBRID MEMORY SERVER
A method, hybrid server system, and computer program product, prefetch data. A set of prefetch requests associated with one or more given datasets residing on...
2016/0239424 HIERARCHICAL PRE-FETCH PIPELINING IN A HYBRID MEMORY SERVER
A method, hybrid server system, and computer program product, prefetch data. A set of prefetch requests associated with one or more given datasets residing on...
2016/0239423 MANAGED MEMORY CACHE WITH APPLICATION-LAYER PREFETCHING
In order to prevent data thrashing and the resulting performance degradation, a computer system may maintain an application-layer cache space to more...
2016/0239422 EXTERNAL MEMORY TAGGING AND STACK ORDERING OF MEMORY TAGS
A cache system includes a processor chip to receive a processing unit address. The cache system also includes a comparator to compare the processing unit...
2016/0239421 MEMORY NEST EFFICIENCY WITH CACHE DEMAND GENERATION
Embodiments of the disclosure relate to optimizing a memory nest for a workload. Aspects include an operating system determining the cache/memory footprint of...
2016/0239420 SYSTEM AND METHOD FOR MANAGING A CACHE POOL
In one embodiment, a system includes a processor and a memory communicatively coupled to the processor. The processor is configured to receive a write request...
2016/0239419 MEMORY NEST EFFICIENCY WITH CACHE DEMAND GENERATION
Embodiments of the disclosure relate to optimizing a memory nest for a workload. Aspects include an operating system determining the cache/memory footprint of...
2016/0239418 EARLY SHARED RESOURCE RELEASE IN SYMMETRIC MULTIPROCESSING COMPUTER SYSTEMS
In one embodiment, a computer-implemented method includes detecting a cache miss for a cache line. A resource is reserved on each of one or more remote...
2016/0239417 SYSTEM AND METHOD FOR UPDATING DATA IN A CACHE
In one embodiment, a computing system includes a cache having one or more memories and a cache manager. The cache manager is able to receive a request to write...
2016/0239416 Methods for Reading Data from a Storage Unit of a Flash Memory and Apparatuses Using the Same
A method for reading data from a storage unit of a flash memory, performed by a processing unit, including at least the following steps: A first read command...
2016/0239415 REMOTE MEMORY ACCESS FUNCTIONALITY IN A CLUSTER OF DATA PROCESSING NODES
A server apparatus comprises a plurality of server on a chip (SoC) nodes interconnected to each other through a node interconnect fabric. Each one of the SoC...
2016/0239414 PARALLEL GARBAGE COLLECTION IMPLEMENTED IN HARDWARE
Embodiments of the invention provide a method and system for dynamic memory management implemented in hardware. In an embodiment, the method comprises storing...
2016/0239413 Garbage Collection Control in Managed Code
Controlling garbage collection operations. The method includes setting up garbage collection to collect objects that are no longer in use in a managed code...
2016/0239412 STORAGE APPARATUS AND INFORMATION PROCESSING SYSTEM INCLUDING STORAGE APPARATUS
A storage apparatus comprises a plurality of storage devices that form a storage volume, a data buffer, and a first control unit that controls the storage...
2016/0239411 TECHNIQUES FOR CONTROLLING RECYCLING OF BLOCKS OF MEMORY
The present disclosure relates to examples of controlling recycling of blocks of memory. In one example implementation according to aspects of the present...
2016/0239410 ACCELERATING MULTIVERSION CONCURRENCY CONTROL USING HARDWARE TRANSACTIONAL MEMORY
Atomically updating shared data in a transactional memory system comprising transactional memory storage and a transactional memory enabled processor. The...
2016/0239409 TESTING A WEB SERVICE USING INHERITED TEST ATTRIBUTES
A method for testing a web service using inherited test attributes is described. The method includes generating a test template for a web service entry point,...
2016/0239408 PROFILING SYSTEM FOR COMPUTING DEVICES
Systems and methods for profiling application code are disclosed. The method is hybrid in nature as it may include inserting instrumentation within application...
2016/0239407 SMALL SCALE INTEGRATION TEST GENERATION
Provided are methods and systems for automated generation of small scale integration tests to keep mocked input-output contract expectations of external...
2016/0239406 Identity Propagation through Application Layers Using Contextual Mapping and Planted Values
Mechanisms are provided for propagating source identification information from an application front-end system in an application layer to a data layer...
2016/0239405 DEBUGGING OF A DATA PROCESSING APPARATUS
A data processing apparatus is provided comprising data processing circuitry and debug circuitry. The debug circuitry controls operation of the processing...
2016/0239404 APPARATUS AND METHOD FOR CONTROLLING DEBUGGING OF PROGRAM INSTRUCTIONS INCLUDING A TRANSACTION
An apparatus and method are provided for controlling debugging of program instructions executed on processing circuitry, where the program instructions include...
2016/0239403 AN APPARATUS AND METHOD FOR CONTROLLING DEBUGGING OF PROGRAM INSTRUCTIONS INCLUDING A TRANSACTION
An apparatus and method are provided for controlling debugging of program instructions that include a transaction, where the transaction is executed on...
2016/0239402 SOFTWARE COMMIT RISK LEVEL
A risk level of a software commit is assessed through the use of a classifier. The classifier may be generated based on attributes pertaining to previous...
2016/0239401 BLACK-BOX SOFTWARE TESTING WITH STATISTICAL LEARNING
A method to determine a relationship between inputs and outputs based on a parametric model may include receiving a data set that includes known inputs and...
2016/0239400 EMBEDDING AND EXECUTING TRACE FUNCTIONS IN CODE TO GATHER TRACE DATA
Provided are a computer program product, system, and method for embedding and executing trace functions in code to gather trace data. A plurality of trace...
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