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SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
According to one embodiment, it includes a stacked body formed such that a first layer and a second layer, which are made of materials different from each...
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device and a manufacturing method of a semiconductor device thereof are provided. The manufacturing method includes the following steps. Two...
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device and a manufacturing method of a semiconductor device thereof are provided. The manufacturing method includes the following steps. A...
PATTERN LAYOUT TO PREVENT SPLIT GATE FLASH MEMORY CELL FAILURE
A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a first...
SEMICONDUCTOR STRUCTURE INCLUDING A SPLIT GATE NONVOLATILE MEMORY CELL AND
A HIGH VOLTAGE TRANSISTOR, AND...
A semiconductor structure includes a split gate nonvolatile memory cell and a high voltage transistor. The nonvolatile memory cell includes an active region, a...
SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE
SEMICONDUCTOR STORAGE DEVICE
A semiconductor storage device includes an insulating layer. A ferroelectric capacitor is on the insulating layer and includes a lower electrode, a...
SEMICONDUCTOR MEMORY DEVICE
The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate,...
Provided is a technology for further reducing a loss in a semiconductor device including a semiconductor substrate in which an IGBT region and a diode region...
FIN FIELD EFFECT TRANSISTOR
Various embodiments provide semiconductor devices and methods for forming the same. A first fin and a second fin are formed on a semiconductor substrate. A...
METHOD OF CO-INTEGRATION OF STRAINED SILICON AND STRAINED GERMANIUM IN
SEMICONDUCTOR DEVICES INCLUDING FIN...
A method of forming a semiconductor device that includes forming an at least partially relaxed semiconductor material, and forming a plurality of fin trenches...
METHOD OF FORMING A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR STRUCTURE WITH
N-TYPE AND P-TYPE FIELD EFFECT...
In a method of forming a semiconductor structure, different sections of a dielectric layer are etched at different stages during processing to form a first...
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE
Provided is a semiconductor integrated circuit device including a first N-channel type high withstanding-voltage MOS transistor and a second N-channel type...
A semiconductor device includes a semiconductor substrate having an active layer in which an element region and a contact region are formed, a support...
ELECTRODE STRUCTURE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR
DEVICE INCLUDING THE ELECTRODE STRUCTURE
An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second...
METHOD FOR FORMING DEEP TRENCH ISOLATION FOR RF DEVICES ON SOI
A semiconductor device includes a silicon-on-insulator (SOI) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a...
DUAL-SERIES VARACTOR EPI
A semiconductor device includes a first varactor diode and a second varactor diode. The second varactor diode is coupled in series with the first varactor...
TRANSISTOR BODY CONTROL CIRCUIT AND AN INTEGRATED CIRCUIT
An integrated circuit comprises a transistor body control circuit for controlling a body of a bidirectional power transistor. The transistor body control...
A semiconductor device includes a package, an input terminal fixed to the package, an input pre-matched substrate provided in the package, a semiconductor...
LAYOUT STRUCTURE OF HETEROJUNCTION BIPOLAR TRANSISTORS
A layout structure of HBTs comprising one or more HBTs, each of which comprises a base electrode, an emitter electrode, and a collector electrode. A passive...
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of...
AVALANCHE ENERGY HANDLING CAPABLE III-NITRIDE TRANSISTORS
A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a...
Compound Semiconductor Transistor with Gate Overvoltage Protection
A transistor device includes a compound semiconductor body, a drain disposed in the compound semiconductor body and a source disposed in the compound...
SEMICONDUCTOR MODULE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING
A semiconductor module includes: first semiconductor devices; second semiconductor devices; a first and second wires. Each first semiconductor device...
SWITCH CIRCUIT OF CASCODE TYPE HAVING HIGH SPEED SWITCHING PERFORMANCE
Provided is switch circuit including first and second transistors, a source pad connected to a second node of the second transistor through a first signal path...
SEMICONDUCTOR CHIP STACKING ASSEMBLIES
Embodiments of the invention provide semiconductor chip stacking assemblies that provide direct attachment of a first semiconductor device with a second...
Alignment in the Packaging of Integrated Circuits
A method includes aligning a top package to a bottom package using an alignment mark in the bottom package, and placing the top package over the bottom...
METHOD OF ARRANGING A MULTIPLICITY OF LEDS IN PACKAGING UNITS, AND
PACKAGING UNIT INCLUDING A MULTIPLICITY OF LEDS
A method of arranging a multiplicity of LEDs in packaging units includes defining a desired range for at least one photometric measurement variable for each of...
HIGH-VOLTAGE LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF
The disclosure relates to a high-voltage light-emitting diode (HV LED) and a manufacturing method thereof. A plurality of LED dies connected in series, in...
LIGHT-EMITTING DIODE CHIP PACKAGE
A light-emitting diode chip package is provided. The light-emitting diode chip package includes a substrate; a light-emitting diode chip set (LED chip set)...
Packages with Stacked Dies and Methods of Forming the Same
A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first...
Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication...
METHOD AND APPARATUS FOR INTERCONNECTING STACKED DIES USING METAL POSTS
Embodiments include a semiconductor package comprising a first die having (i) a first side and (ii) a second side, wherein the first die comprises a first...
A semiconductor device includes a semiconductor layer and a first insulating film provided on the semiconductor layer. The first insulating film has a surface...
PACKAGE-ON-PACKAGE STRUCTURE HAVING POLYMER-BASED MATERIAL FOR WARPAGE
A package on package structure providing mechanical strength and warpage control includes a first package component coupled to a second package component by a...
Semiconductor packages are provided. A semiconductor package may include an embedding substrate including a cavity therein and a connection window in a bottom...
Method of Manufacturing a Semiconductor Package Having an Integrated
A method of manufacturing an array of semiconductor device packages includes placing a plurality of semiconductor chips on a temporary carrier, covering the...
CHIP-ON-WAFER PACKAGE AND METHOD OF FORMING SAME
A package according to an embodiment includes a first device package and a fan-out RDL disposed over the first device package. The fan-out RDL extends past...
Localized sealing of interconnect structures in small gaps
An apparatus relates generally to a microelectronic device. In such an apparatus, a first substrate has a first surface with first interconnects located on the...
WIRE BONDING METHOD
A wire bonding method includes the following steps. First, a substrate including at least one metal finger is provided. Next, a first chip including at least...
ELECTRONIC APPARATUS AND METHOD FOR FABRICATING THE SAME
An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal,...
CHIP PACKAGING STRCUTRE AND MANUFATURING METHOD THEREOF
A chip packaging structure including a substrate, at least one chip, a plurality of conductive bumps, and an electrically insulating and thermally conductive...
INTEGRATED WLUF AND SOD PROCESS
This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the...
METHOD FOR FABRICATING PACKAGE STRUCTURE
A package structure is disclosed, which includes a substrate having a body, a plurality of conductive pads formed on the body and a surface passivation layer...
MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICES
A manufacturing method for semiconductor devices includes the steps of forming an Ni/Au film that includes an Ni film and an Au film formed over the Ni film...
A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip...
ON-CHIP SEMICONDUCTOR DEVICE HAVING ENHANCED VARIABILITY
A physical unclonable function (PUF) semiconductor device includes a semiconductor substrate extending along a first direction to define a length and a second...
APPARATUS AND METHOD FOR GENERATING IDENTIFICATION KEY
Provided is an apparatus for generating an identification key by using process variation in a conductive layer manufacturing process. The apparatus may include...
APPARATUS AND METHOD FOR GENERATING IDENTIFICATION KEY
An apparatus for generating an identification key is provided. The apparatus may include a first conductive layer formed on a semiconductor chip, a second...
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
A semiconductor package and a method of manufacturing a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various...
REGISTRATION MARK FORMATION DURING SIDEWALL IMAGE TRANSFER PROCESS
Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may...