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Patent # Description
2016/0247765 SEMICONDUCTOR DEVICE, PLATING METHOD, PLATING SYSTEM AND RECORDING MEDIUM
Adhesivity between a catalyst adsorption layer on a substrate and a barrier metal plating layer can be improved. The catalyst adsorption layer 22 containing a...
2016/0247764 Substrate-to-carrier adhesion without mechanical adhesion between abutting surfaces thereof
Wafer to carrier adhesion without mechanical adhesion for formation of an IC. In such formation, an apparatus has a bottom surface of a substrate abutting a...
2016/0247763 METHOD FOR MAKING HIGH DENSITY SUBSTRATE INTERCONNECT USING INKJET PRINTING
Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a...
2016/0247762 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
In one embodiment, a semiconductor device includes a substrate. The device further includes a first interconnect which includes a first layer provided on the...
2016/0247761 INTEGRATED DEVICE PACKAGE COMPRISING CONDUCTIVE SHEET CONFIGURED AS AN INDUCTOR IN AN ENCAPSULATION LAYER
An integrated device package includes a package substrate, a die coupled to the package substrate, an encapsulation layer encapsulating the die, and at least...
2016/0247760 SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes a dielectric structure which has an opening exposing a surface of a substrate; and a conductive structure which is formed in...
2016/0247759 SEMICONDUCTOR DEVICES HAVING STAGGERED AIR GAPS
A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns...
2016/0247758 MICROELECTRONIC ASSEMBLIES FORMED USING METAL SILICIDE, AND METHODS OF FABRICATION
Two microelectronic components (110, 120), e.g. a die and an interposer, are bonded to each other. One of the components' contact pads (110C) include metal,...
2016/0247757 Capacitor in Post-Passivation Structures and Methods of Forming the Same
A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying...
2016/0247756 CAPPING POLY CHANNEL PILLARS IN STACKED CIRCUITS
A three dimensional or stacked circuit device includes a conductive channel cap on a conductor channel. The channel cap can be created via selective deposition...
2016/0247755 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
In one embodiment, a method of manufacturing a semiconductor device includes forming a plug in a first insulator, forming a first film on the first insulator...
2016/0247754 CONDUCTIVE POST PROTECTION FOR INTEGRATED CIRCUIT PACKAGES
An integrated circuit package includes a substrate/interposer assembly having a plurality of conductive contacts and a plurality of conductive posts, such as...
2016/0247753 CAVITY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a cavity substrate of the present invention includes respectively laminating second and third substrates on upper and lower surfaces...
2016/0247752 Compensation Of Bondwires In The Microwave Regime
A method for connecting an integrated circuit (IC) to a printed circuit board (PCB) can include the steps of fixing the IC and the PCB to a dielectric...
2016/0247751 LEADLESS ELECTRONIC PACKAGES FOR GAN DEVICES
Leadless electronic packages for GaN-based half bridge power conversion circuits have low inductance internal and external connections, high thermal...
2016/0247750 PROCESS FOR MANUFACTURING A 3D ELECTRONIC MODULE COMPRISING EXTERNAL INTERCONNECTION LEADS
A process for manufacturing at least one 3D electronic module each comprises a stack of electronic packages and/or printed wiring boards, wherein a stack is...
2016/0247749 SEMICONDUCTOR DIES WITH RECESSES, ASSOCIATED LEADFRAMES, AND ASSOCIATED SYSTEMS AND METHODS
Semiconductor dies with recesses, associated leadframes, and associated systems and methods are disclosed. A semiconductor system in accordance with one...
2016/0247748 ELECTRONIC PACKAGES FOR FLIP CHIP DEVICES
Electronic packages are formed from a generally planar leadframe having a plurality of leads coupled to a GaN-based semiconductor device, and are encased in an...
2016/0247747 DISABLING ELECTRICAL CONNECTIONS USING PASS-THROUGH 3D INTERCONNECTS AND ASSOCIATED SYSTEMS AND METHODS
Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are...
2016/0247746 SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE
There is provided a method for manufacturing a semiconductor device including a first semiconductor base substrate, a second semiconductor base substrate that...
2016/0247745 Semiconductor Structure Including a Thermally Conductive, Electrically Insulating Layer
A thermally conductive and electrically insulating layer is provided over a semiconductor structure.
2016/0247744 HEAT SPREADER AND METHOD FOR FORMING
The present disclosure provides embodiments for a semiconductor structure including a heat spreader that includes a graphene grid having a first major surface...
2016/0247743 SEMICONDUCTOR MODULE
A semiconductor module has a structure in which a semiconductor device, an insulating sheet, and a cooler are stacked on each other. The semiconductor device...
2016/0247742 APPARATUSES AND METHODS FOR SEMICONDUCTOR DIE HEAT DISSIPATION
Apparatuses and methods for semiconductor die heat dissipation are described. For example, an apparatus for semiconductor die heat dissipation may include a...
2016/0247741 SYSTEMS AND METHODS TO ENHANCE PASSIVATION INTEGRITY
A semiconductor device is disclosed in some embodiments. The device includes a substrate, and a layer disposed over the substrate. The layer includes an...
2016/0247740 COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A compound semiconductor device includes a first protection film which covers a surface of a compound semiconductor layer, where the first protection film is...
2016/0247739 BONDED SYSTEM AND A METHOD FOR ADHESIVELY BONDING A HYGROSCOPIC MATERIAL
A bonded system includes a reconstituted wafer including a hygroscopic material. A moisture barrier layer is arranged over a surface of the reconstituted...
2016/0247738 INTEGRATED CIRCUIT CARRIER COATING
A device includes an integrated circuit (IC) carrier for a semiconductor device, and a coating on the IC carrier. In the presence of an electrical field or a...
2016/0247737 NOVEL BUILD-UP PACKAGE FOR INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME
A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a...
2016/0247736 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE
A semiconductor device includes a housing with a fragile portion. The fragile unit or portion has a resistance to a pressure or a melting point temperature...
2016/0247735 SEMICONDUCTOR PACKAGE WITH ELASTIC COUPLER AND RELATED METHODS
A semiconductor package includes: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of...
2016/0247734 METHOD OF MANUFACTURING ORGANIC EL DISPLAY APPARATUS, AND INSPECTION APPARATUS
A method of manufacturing an organic EL display apparatus including an organic EL panel having light emitting pixels each of which has an organic EL element...
2016/0247733 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND PROBE CARD
Reliability of an electrical test of a semiconductor wafer is improved. A method of manufacturing a semiconductor device includes a step of performing an...
2016/0247732 ELECTRONIC DEVICES INCLUDING ORGANIC MATERIALS
A method comprising forming on a common support (6) one or more series of multi-layer electronic devices (covering the areas 2a, 2b respectively), and then...
2016/0247731 MULTIPLE THRESHOLD VOLTAGE TRIGATE DEVICES USING 3D CONDENSATION
A method of forming a multiple threshold voltage p-channel silicon germanium trigate device using (3D) condensation. The method may include forming a first and...
2016/0247730 METHODS OF FABRICATING SEMICONDUCTOR DEVICES INCLUDING HARD MASK PATTERNING
Methods of fabricating semiconductor devices may include forming an isolation region that defines a plurality of fin active regions on a semiconductor...
2016/0247729 Semiconductor Device and Method of Manufacturing the Same
A semiconductor device includes: a first silicon section G1 which contains a p-type impurity and is a gate electrode G of a p-channel type MISFET 1P; a second...
2016/0247728 METHOD OF FABRICATING SEMICONDUCTOR DEVICE
A method of fabricating a semiconductor device includes forming a first well region and a second well region in a semiconductor substrate, forming an isolation...
2016/0247727 REPLACEMENT METAL GATES TO ENHANCE TRANSISTOR STRAIN
Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.
2016/0247726 METHOD FOR FABRICATING A QUASI-SOI SOURCE-DRAIN MULTI-GATE DEVICE
The present invention discloses a method for fabricating a quasi SOI source-drain multi-gate device, belonging to a field of manufacturing ultra large scale...
2016/0247725 FINE PATTERNING METHODS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES USING THE SAME
A fine-patterning method includes forming a mask layer with lower and upper mask layers on an underlying layer, forming a pair of sacrificial patterns on the...
2016/0247724 METHOD, APPARATUS AND SYSTEM FOR ADVANCED CHANNEL CMOS INTEGRATION
At least one method, apparatus and system disclosed involves a semiconductor substrate on which NMOS and PMOS devices with enhanced current drives may be...
2016/0247723 WAFER DIVIDER AND WAFER DIVISION METHOD
A divider which divides a wafer having a division start points formed along the scheduled divisions into a plurality of device chips. The divider includes a...
2016/0247722 INTERCONNECT STRUCTURE HAVING LARGE SELF-ALIGNED VIAS
A wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using...
2016/0247721 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A method for manufacturing a semiconductor device is provided. The method includes the following operations: (i) forming a transistor having a source, a drain...
2016/0247720 Top Metal Pads as Local Interconnectors of Vertical Transistors
An integrated circuit structure includes a first vertical transistor and a second vertical transistor. The first vertical transistor includes a first...
2016/0247719 Semiconductor Devices And Fabrication Methods With Improved Word Line Resistance and Reduced Salicide Bridge...
Provided are improved semiconductor memory devices and method for manufacturing such semiconductor memory devices. A method may incorporate the formation of...
2016/0247718 METHOD OF ENABLING SEAMLESS COBALT GAP-FILL
Methods for depositing a contact metal layer in contact structures of a semiconductor device are provided. In one embodiment, a method for depositing a contact...
2016/0247717 METHOD FOR PROCESSING AN ELECTROPLATED COPPER FILM IN COPPER INTERCONNECT PROCESS
A method for processing an electroplated copper film in copper interconnect process is disclosed by the present invention. Firstly, in the copper...
2016/0247716 METAL LINES HAVING ETCH-BIAS INDEPENDENT HEIGHT
A dielectric material stack including at least a via level dielectric material layer, at least one patterned etch stop dielectric material portion, a line...
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