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Patent # Description
2016/0254256 SYSTEM-ON-CHIP DEVICES AND METHODS OF DESIGNING A LAYOUT THEREFOR
A system-on-chip device may include a substrate with an active pattern, a gate electrode crossing the active pattern and extending in a first direction, and a...
2016/0254255 POWER SEMICONDUCTOR MODULE AND COMPOSITE MODULE
A power semiconductor module includes a wiring member that electrically connects a front surface electrode of a semiconductor element and a circuit board of an...
2016/0254254 SEMICONDUCTOR LIGHT EMITTING DEVICE
A light emitting device includes a substrate, a light emitting element mounted on the substrate, a light transmissive member placed on an upper surface of the...
2016/0254253 Method for Producing a Semiconductor Component and a Semiconductor Component
A method for producing a plurality of semiconductor components and a semiconductor component are disclosed. In an embodiment the method includes applying a...
2016/0254252 SYSTEMS AND METHODS FOR BONDING SEMICONDUCTOR ELEMENTS
A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first...
2016/0254251 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate, an elastic buffer layer disposed on a surface of the substrate, wiring patterns disposed on a first surface of the...
2016/0254250 SEMICONDUCTOR MODULE
A semiconductor module according to one embodiment of the present invention includes: a first circuit board having thermal conductivity; a second circuit board...
2016/0254249 3D Semiconductor Package Interposer with Die Cavity
Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or...
2016/0254248 Integrated Circuit Structure with Active and Passive Devices in Different Tiers
An integrated circuit structure includes a two-tier die including a first tier and a second tier over and bonded to the first tier. The first tier includes a...
2016/0254247 Fan-out WLP with package
Described herein are microelectronic packages and methods of making such packages. Consistent with an example embodiment, the package includes a ...
2016/0254246 APPARATUS AND METHOD FOR BONDING CHIPS
An apparatus and method for bonding chips (4) is disclosed. The apparatus for bonding chips (4) comprises: a base stage (1) and a press head (2), the side of...
2016/0254245 BOND HEAD ASSEMBLIES, THERMOCOMPRESSION BONDING SYSTEMS AND METHODS OF ASSEMBLING AND OPERATING THE SAME
A bond head assembly for bonding a semiconductor element to a substrate is provided. The bond head assembly includes a base structure, a heater, and a clamping...
2016/0254244 Systems and Methods Utilizing Anisotropic Conductive Adhesives
Illustrative embodiments of systems and method utilizing anisotropic conductive adhesive(s) ("ACA") are disclosed. In at least one illustrative embodiment, a...
2016/0254243 JOINING SILVER SHEET, METHOD FOR MANUFACTURING SAME, AND METHOD FOR JOINING ELECTRONIC PART
A joining silver sheet with high joining strength contains silver particles having a particle diameter of from 1 to 250 nm integrated by sintering, and has a...
2016/0254242 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a semiconductor substrate, a pad, a circuit board, a first bump, and a second bump. The pad is disposed on a top surface of...
2016/0254241 PRINTED CIRCUIT BOARD AND SOLDERING METHOD
A printed circuit board includes: a substrate; a first electrode formed on the substrate; a protrusion member formed on the first electrode and extending from...
2016/0254240 Interconnect Structures, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices
Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, an interconnect...
2016/0254239 METHOD OF MANUFACTURING MICRO PINS AND ISOLATED CONDUCTIVE MICRO PIN
A method of manufacturing micro pins includes forming a release layer over a substrate. A pattern layer is formed over the release layer, in which the pattern...
2016/0254238 Packaging Devices and Methods of Manufacture Thereof
Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad...
2016/0254237 RADIO-FREQUENCY (RF) SHIELDING IN FAN-OUT WAFER LEVEL PACKAGE (FOWLP)
Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a fan-out wafer level package...
2016/0254236 COMPARTMENT SHIELDING IN FLIP-CHIP (FC) MODULE
Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a multichip module or device,...
2016/0254235 SEMICONDUCTOR DEVICE SECURITY
Semiconductor device security is provided as follows. A unique identification is generated by randomly forming a plurality of defects in one or more circuit...
2016/0254234 DUMMY METAL STRUCTURE AND METHOD OF FORMING DUMMY METAL STRUCTURE
Methods for forming a dummy metal structure between dies on a semiconductor wafer and the resulting devices are disclosed. Embodiments may include forming...
2016/0254233 COMPOSITE CARRIER FOR WARPAGE MANAGEMENT
A composite carrier is disclosed for warpage management as a temporary carrier in semiconductor process. Warpage is reduced for a product, semi-product, or...
2016/0254232 Combined wafer production method with laser treatment and temperature-induced stresses
The present invention relates to a method for the production of layers of solid material. The method according to the invention comprises at the very least the...
2016/0254231 Methods of Making Integrated Circuit Assembly with Faraday Cage
An integrated circuit assembly is formed with an insulating layer, a semiconductor layer, an active device, first, second, and third electrically conductive...
2016/0254230 SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
The present disclosure relates to a semiconductor device package and a manufacturing method thereof. The semiconductor package comprises a die pad, a row of...
2016/0254229 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a plurality of devices, each of the plurality of devices includes a first surface disposed with an active component; and a...
2016/0254228 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Product management and/or prompt defect analysis of a semiconductor device may be carried out without reducing the throughput in assembly and testing. Unique...
2016/0254227 SEMICONDUCTOR DEVICE SECURITY
Semiconductor device security is provided as follows. A unique identification is generated by randomly forming a plurality of defects in one or more circuit...
2016/0254226 CAPPING LAYER FOR IMPROVED DEPOSITION SELECTIVITY
The present disclosure relates to an integrated chip having a back-end-of-the-line (BEOL) metal interconnect structure with capping layers that provide for...
2016/0254225 COPPER ETCHING INTEGRATION SCHEME
The present disclosure is directed to an integrated circuit. The integrated circuit has a conductive body disposed over a substrate. The conductive body has...
2016/0254224 INDUCTOR FOR SEMICONDUCTOR INTEGRATED CIRCUIT
An inductor includes a plurality of first conductive lines, a plurality of second conductive lines and a plurality of contacts. Each of the first conductive...
2016/0254223 Coarse Grid Design Methods and Structures
A layer of a mask material is deposited on a substrate. A beam of energy is scanned across the mask material in a rasterized linear pattern and in accordance...
2016/0254222 METALLIZATION OF THE WAFER EDGE FOR OPTIMIZED ELECTROPLATING PERFORMANCE ON RESISTIVE SUBSTRATES
A system for electroless deposition on a substrate is provided, including the following: a chamber; a substrate support configured to receive a substrate...
2016/0254221 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
A semiconductor package and a method of making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various...
2016/0254220 LOW WARPING CORELESS SUBSTRATE AND SEMICONDUCTOR ASSEMBLY USING THE SAME
A coreless substrate includes a build-up circuitry, a warping controller and an optional stiffener. The warping controller is adhered to the solder ball...
2016/0254219 TAPE FOR ELECTRONIC DEVICES WITH REINFORCED LEAD CRACK
Provided is a tape for electronic devices with lead crack and a method of manufacturing the tape. According to the present invention, by forming a bending...
2016/0254218 PACKAGING MODULE OF POWER CONVERTING CIRCUIT AND METHOD FOR MANUFACTURING THE SAME
The disclosure discloses a packaging module of a power converting circuit and a method for manufacturing the same. The packaging module of the power converting...
2016/0254217 PACKAGE MODULE OF POWER CONVERSION CIRCUIT AND MANUFACTURING METHOD THEREOF
The present disclosure discloses a package module of a power conversion circuit and a manufacturing method thereof. The package module of the power conversion...
2016/0254216 INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING THE SAME
A method of making an integrated circuit package includes: (a) forcing a circuit layered structure that includes a metal substrate and a circuit pattern, the...
2016/0254215 SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SAME
A terminal case formed by integrally molding a lead frame and a case that has internally an inner face on which the lead frame is mounted and has externally a...
2016/0254214 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
In a method of manufacturing a semiconductor device according to an embodiment, a lead frame is provided, the lead frame having a trench part formed thereon so...
2016/0254213 STACK PACKAGE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING A VARIABLE VOLTAGE
A stack package may include a first chip, a second chip, a through silicon via (TSV) and an interface circuit unit. The first chip may include a first internal...
2016/0254212 ONBOARD ELECTRONIC DEVICE
An onboard electronic device includes: an element that generates heat; a member that is provided between the element and a coolant cooling the element, and...
2016/0254211 Thermal Structure for Integrated Circuit Package
One or more heat pipes are utilized along with a substrate in order to provide heat dissipation through the substrate for heat that can build up at an...
2016/0254210 SUPPORT FOR ELECTRONIC POWER COMPONENTS, POWER MODULE PROVIDED WITH SUCH A SUPPORT, AND CORRESPONDING...
This substrate for power electronic components comprises a colaminated multilayer composite material containing at least one internal layer (8) made of a...
2016/0254209 POWER-MODULE SUBSTRATE WITH HEAT-SINK AND MANUFACTURING METHOD THEREOF
A maximum length of a heat sink is set as "L" and a warp amount of the heat sink is set as "Z"; the warp amount "Z" is set as a positive value if a bonded...
2016/0254208 INTEGRATED CIRCUIT BARRIERLESS MICROFLUIDIC CHANNEL
A structure and method for fabricating a continuous cooling channel in the back end of line wiring levels of an integrated circuit (IC) chip is provided. This...
2016/0254207 Directional Heat Dissipation Assembly and Method
A directional heat diffusion assembly and method helps self-cool a transistor by forcing directional heat flow from a heat source, such as from a transistor,...
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