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In a power converter, a plurality of semiconductor devices and a plurality of cooling plates are stacked. The plurality of semiconductor devices includes a...
DEVICE AND METHOD FOR LOCALIZED UNDERFILL
A device and method for localizing underfill includes a substrate, a plurality of dies, and underfill material. The substrate includes a plurality of contacts...
PACKAGED SEMICONDUCTOR COMPONENTS HAVING SUBSTANTIALLY RIGID SUPPORT
MEMBERS AND METHODS OF PACKAGING...
Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member...
Semiconductor Package Having a Multi-Layered Base
A semiconductor package for mounting to a printed circuit board (PCB) includes a semiconductor die in a ceramic case, a conductive base coupled to the...
Array Formed From A Multiplicity Of Electric Integrated Circuits, and
Method For Production Thereof
A method for producing an array formed from a multiplicity of electric integrated circuits, said array being intended for separation and having a conductive...
SEMICONDUCTOR TEST PAD WITH STACKED THIN METAL SHEETS AND METHOD FOR
MANUFACTURING THE SAME
The present invention relates to a semiconductor test pad used in a semiconductor test, and more specifically, to a semiconductor test pad with stacked metal...
Method for Detecting a Crack in a Semiconductor Body of a Semiconductor
A semiconductor component includes a semiconductor body having a bottom side, a top side spaced distant from the bottom side in a vertical direction, and a...
AN APPARATUS AND METHOD FOR INSPECTING A SEMICONDUCTOR PACKAGE
There is provided an apparatus and method for inspecting a semiconductor package. The apparatus includes at least one 3D camera positioned at a first angle...
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
One embodiment includes a vertical n-channel power MOSFET for an output stage and a horizontal p-channel MOSFET for controlling the vertical n-channel power...
INNER L-SPACER FOR REPLACEMENT GATE FLOW
An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first...
FORMING A CMOS WITH DUAL STRAINED CHANNELS
The present invention relates generally to a semiconductor device, and more particularly, to a structure and method of forming a compressive strained layer and...
METHODS OF MODULATING STRAIN IN PFET AND NFET FINFET SEMICONDUCTOR DEVICES
One illustrative method disclosed herein includes, among other things, forming a plurality of initial fins that have the same initial axial length and the same...
Layout Architecture for Performance Improvement
An integrated circuit is provided. The integrated circuit includes a first contact disposed over a first source/drain region, a second contact disposed over a...
REDUCED CURRENT LEAKAGE SEMICONDUCTOR DEVICE
A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed...
METHODS OF PERFORMING FIN CUT ETCH PROCESSES FOR FINFET SEMICONDUCTOR
DEVICES AND THE RESULTING DEVICES
A method includes forming a plurality of fins above a substrate. A first mask layer is formed above a first subset of the fins. First portions of the fins in...
FIN PATTERNING METHODS FOR INCREASED PROCESS MARGIN
A method for fabricating a semiconductor device includes forming a plurality of first spacers over a substrate. A second spacer of a plurality of second...
Method of Forming Layout Design
A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout...
Method for Dicing a Substrate with Back Metal
The present invention provides a method for dicing a substrate with back metal, the method comprising the following steps. The substrate is provided with a...
WAFER DIVIDING METHOD
A wafer having on one side a device area with devices partitioned by division lines is divided into dies. An adhesive tape for protecting the devices is...
Disposable Pillars for Contact Information
Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various...
METHOD OF FORMING A WRAP-AROUND CONTACT ON A SEMICONDUCTOR DEVICE
Techniques and methods related to forming a wrap-around contact on a semiconductor device, and apparatus, system, and mobile platform incorporating such...
INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH
Integrated circuits and methods for fabricating integrated circuits with self-aligned vias are disclosed. A method for fabricating an integrated circuit...
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD
A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating...
Multi-Layer Metal Contacts
A method for forming metal contacts within a semiconductor device includes forming a first-layer contact into a first dielectric layer that surrounds at least...
Removal Composition for Selectively Removing Hard Mask and Methods Thereof
The present disclosure relates to a method for removing a hard mask consisting essentially of TiN, TaN, TiNxOy, TiW, W, Ti and alloys of Ti and W from a...
ALUMINUM NITRIDE BARRIER LAYER
A method of forming features in a dielectric layer is described. A via, trench or a dual-damascene structure may be present in the dielectric layer prior to...
SELF ALIGNED RAISED FIN TIP END STI TO IMPROVE THE FIN END EPI QUALITY
A method as set forth herein can include patterning using a first mask an isolation trench at a sidewall to sidewall isolation (SSI) region of a semiconductor...
METHOD FOR FABRICATING SHALLOW TRENCH ISOLATION AND SEMICONDUCTOR
STRUCTURE USING THE SAME
A method for fabricating a shallow trench isolation includes forming a trench in a substrate, forming a bottom shallow trench isolation dielectric filling a...
FINFET HAVING CONTROLLED DIELECTRIC REGION HEIGHT
Embodiments are directed to a method of forming a dielectric region of a fin-type field effect transistor (FinFET). The method includes forming at least one...
SEMICONDUCTOR DEVICE WITH VOIDS WITHIN SILICON-ON-INSULATOR (SOI)
STRUCTURE AND METHOD OF FORMING THE...
A semiconductor device with voids within a silicon-on-insulator (SOI) structure and a method of forming the semiconductor device are provided. Voids are formed...
Positive Pressure Bernoulli Wand with Coiled Path
A wand operating under the Bernoulli principle to pick up, transport and deposit wafers, which continuous pattern imposed into the horizontal surface of the...
VACUUM ADSORPTION SYSTEM, METHOD AND PACKAGING DEVICE FOR MOTHER SUBSTRATE
TO BE PACKAGED
Vacuum adsorption system of the invention includes: vacuum adsorption platform; carrying platform, which is provided on vacuum adsorption platform and edges...
SUPPPORTING DEVICE, METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY
SUBSTRATE AND METHOD FOR MANUFACTURING...
A supporting device includes a main body and a ring-shaped glue layer. The main body includes a top surface and a bottom surface opposite to the top surface....
SPATIALLY LIMITED PROCESSING OF A SUBSTRATE
A method of chemical processing includes passing a substrate material from a first transfer conveyor device to a second transfer conveyor device across a fluid...
A front opening wafer container suitable for large wafers such as 450 mm utilizes componentry with separate fasteners to lock the componentry together in an...
IMAGE REVERSAL WITH AHM GAP FILL FOR MULTIPLE PATTERNING
Methods and apparatuses for multiple patterning using image reversal are provided. The methods may include depositing gap-fill ashable hardmasks using a...
METHOD AND SYSTEM FOR CLEANING WAFER AND SCRUBBER
A method of cleaning a wafer in semiconductor fabrication is provided. The method includes cleaning a wafer using a wafer scrubber. The method further includes...
Integrated Circuit Underfill Scheme
An integrated circuit includes a substrate having at least one depression on a top surface. At least one solder bump is disposed over the substrate. A die is...
3D Shielding Case and Methods for Forming the Same
A package includes a die, and a molding material molding the die therein. A metal shield case includes a first metal mesh over and contacting the molding...
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
An object is to manufacture a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for...
Chemical Circulation System and Methods of Cleaning Chemicals
A method includes passing a chemical solution through a metal-ion absorber, wherein metal ions in the metal-ion absorber are trapped by the metal-ion absorber....
SELECTIVE ETCHING PROCESS OF A MASK DISPOSED ON A SILICON SUBSTRATE
The method includes the steps of: a) providing a silicon substrate including a first portion covered by the mask made from a carbonaceous material and a second...
METHOD FOR STRIPPING MODIFIED RESIST, MODIFIED-RESIST STRIPPER USED
THEREFOR, AND METHOD FOR MANUFACTURING...
Provided is a stripping method for stripping a modified resist from a semiconductor substrate by applying an etching solution to the semiconductor substrate,...
PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD
A plasma processing apparatus includes a sample stage disposed in a processing chamber within a vacuum chamber. A wafer mounted on a top surface of the sample...
SACRIFICIAL-FILM REMOVAL METHOD AND SUBSTRATE PROCESSING DEVICE
The present invention is a sacrificial-film removal method of removing a sacrificial film from a surface of a substrate provided with a plurality of struts and...
Method for Patterning an Underlying Layer
A method for patterning an underlying layer is described, the method comprising providing a guiding layer on the underlying layer, the guiding layer comprising...
Method of Manufacturing Semiconductor Device and Semiconductor Device
Reliability of a semiconductor device is improved. A power device includes: a semiconductor chip; a chip mounting part; a solder material electrically coupling...
METHODS OF FORMING MEMORY CELLS WITH AIR GAPS AND OTHER LOW DIELECTRIC
Various embodiments include apparatuses and methods of forming the same. One such apparatus can include a first dielectric material and a second dielectric...
CO-FABRICATION OF NON-PLANAR SEMICONDUCTOR DEVICES HAVING DIFFERENT
Co-fabricating non-planar (i.e., three-dimensional) semiconductor devices with different threshold voltages includes providing a starting semiconductor...
Metal Gate Stack Having TaAlCN Layer
A method includes forming a gate stack over a semiconductor substrate; forming an interlayer dielectric layer surrounding the gate stack; and at least...