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Patent # Description
2016/0261296 TERMINAL DEVICE, BASE STATION APPARATUS, METHOD IN TERMINAL DEVICE, AND METHOD IN BASE STATION APPARATUS
According to an aspect of the present invention, there is provided a terminal device that communicates with a base station apparatus, the terminal device...
2016/0261295 DIGITAL PRE-DISTORTION (DPD) TRAINING AND CALIBRATION SYSTEM AND RELATED TECHNIQUES
A radio frequency (RF) transmit system includes an observation receiver coupled to receive a portion of an RF signal propagating along an RF transmit signal...
2016/0261294 WIDE BANDWIDTH DIGITAL PREDISTORTION SYSTEM WITH REDUCED SAMPLING RATE
A digital predistortion linearization method is provided for increasing the instantaneous or operational bandwidth for RF power amplifiers employed in wideband...
2016/0261293 RADIO FREQUENCY SYSTEM HYBRID POWER AMPLIFIER SYSTEMS AND METHODS
Systems and method for improving operation of a radio frequency system are provided. One embodiment provides a radio frequency system that includes a first...
2016/0261292 HIGH-FREQUENCY MODULE AND MICROWAVE TRANSCEIVER
A high-frequency module according to an embodiment includes a first board, a first device, a second board, a metal core, and a casing. The first board is...
2016/0261291 SERVICE PROVIDER ADAPTIVE VEHICLE ANTENNA
A vehicle may include a plurality of antennas each associated with a different radio frequency; and a modem including a radio-frequency transceiver and an...
2016/0261290 PARALLEL BIT INTERLEAVER
A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the...
2016/0261289 TRANSMITTER AND PARITY PERMUTATION METHOD THEREOF
A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a...
2016/0261288 DATA PROCESSING DEVICE AND DATA PROCESSING METHOD
The present technology relates to a data processing device and a data processing method that make it possible to ensure good communication quality in a data...
2016/0261287 LENGTH AND RATE COMPATIBLE LDPC ENCODER AND DECODER
A method and apparatus for encoding data and for decoding data using LDPC (low density parity check) codes includes providing a mother LDPC matrix of a...
2016/0261286 TRANSMITTER AND METHOD FOR GENERATING ADDITIONAL PARITY THEREOF
A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword...
2016/0261285 TRANSMITTER AND SHORTENING METHOD THEREOF
A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits...
2016/0261284 TRANSMITTER AND PUNCTURING METHOD THEREOF
A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode outer-encoded bits to generate an LDPC...
2016/0261283 TRANSMITTER AND SHORTENING METHOD THEREOF
A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits...
2016/0261282 TRANSMITTER AND PARITY PERMUTATION METHOD THEREOF
A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a...
2016/0261281 TRANSMITTER AND PARITY PERMUTATION METHOD THEREOF
A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a...
2016/0261280 TRANSMITTER AND SEGMENTATION METHOD THEREOF
A transmitter is provided. The transmitter includes: a segmenter configured to segment information bits into a plurality of blocks based on one of a plurality...
2016/0261279 TRANSMITTER AND PARITY PERMUTATION METHOD THEREOF
A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a...
2016/0261278 DATA COMPRESSION SYSTEMS AND METHOD
Data compression using a combination of content independent data compression and content dependent data compression. In one aspect, a system for compressing...
2016/0261277 MULTI-MODE DISCRETE-TIME DELTA-SIGMA MODULATOR POWER OPTIMIZATION USING SPLIT-INTEGRATOR SCHEME
A method and an apparatus for splitting a switched capacitor integrator of a delta-sigma modulator are provided. The apparatus configures a first integrator...
2016/0261276 D/A CONVERSION CIRCUIT
A D/A converter is configured to output tri-level potentials from an output terminal. A high potential terminal and the output terminal are connected through a...
2016/0261275 HIGH-RELIABILITY HOLDOVER METHOD AND TOPOLOGIES
System and methods for a clock system disciplined to an external reference. In one embodiment, the clock includes a flywheel oscillator controlled by the...
2016/0261274 DYNAMIC CLOCK RATE CONTROL FOR POWER REDUCTION
A pipeline system may adjust clock rates of variable-rate clock signals sent to different processing circuit blocks in a pipeline based on their respective,...
2016/0261273 FREQUENCY DIVIDING APPARATUS AND RELATED METHOD
A frequency dividing apparatus includes: a plurality of latching devices arranged to selectively generate an output signal having a first oscillating frequency...
2016/0261272 ELECTRONIC DEVICE
A novel electronic device including a reconfigurable circuit is provided. In the electronic device including a reconfigurable circuit capable of executing...
2016/0261271 SEMICONDUCTOR DEVICE
A novel programmable logic device is provided. Programmable switches each include a first transistor and a second transistor. The first transistor in a first...
2016/0261270 LEVEL SHIFTER AND NON-VOLATILE MEMORY DEVICE USING THE SAME
The level shifter of an embodiment includes a first level shifter configured to output an intermediate signal wherein a high voltage is a positive supply...
2016/0261269 DUAL POWER SWING PIPELINE DESIGN WITH SEPARATION OF COMBINATIONAL AND SEQUENTIAL LOGICS
A three-dimensional integrated circuit having a dual or multiple power domain is capable of less energy consumption operation under a given clock rate, which...
2016/0261268 Processing Electromagnetic Interference Signal Using Machine Learning
In one embodiment, a method includes receiving, by an electrode of a device, a signal from a user's body. The received signal is based on an electromagnetic...
2016/0261267 APPARATUS AND METHODS FOR RADIO FREQUENCY PIN DIODE SWITCHES
Apparatus and methods for radio frequency (RF) PIN diode switches are provided herein. In certain configurations, one or more PIN diode switches are integrated...
2016/0261266 Electronic Circuit
In accordance with an embodiment, a method includes driving a transistor device by a driver having an output coupled to a control node of the transistor...
2016/0261265 RF Circuit with Switch Transistor with Body Connection
In some method and apparatus embodiments, an RF circuit comprises a switch transistor having a source, a drain, a gate, and a body. A gate control voltage is...
2016/0261264 ZERO-CURRENT POR CIRCUIT
A power-on reset (POR) circuit includes an RC circuit; a Schmitt trigger, an inverter, and a first PMOS tube. A power supply voltage charges a capacitor...
2016/0261263 ANALOG SWITCH CIRCUIT
An analog switch circuit is disclosed. The analog switch circuit includes a MOSFET and a control switch. The MOSFET includes a drain electrode, a source...
2016/0261262 RF Circuit with Switch Transistor with Body Connection
In some method and apparatus embodiments, an RF circuit comprises a switch transistor having a source, a drain, a gate, and a body. A gate control voltage is...
2016/0261261 Methods and Apparatus for a Burst Mode Charge Pump Load Switch
A fully integrated circuit configuration that can be used to control the gate voltage of a power NMOS load switch using a unique method of controlling the...
2016/0261260 INPUT BUFFER CIRCUIT
An input buffer circuit comprising: a first current source; a first differential control circuit, configured to generate a first bias voltage at the first...
2016/0261259 Voltage Detector and Method for Detecting Voltage
A voltage detector includes a comparison unit which is equipped with a plurality of comparators and which is configured to compare a threshold voltage and...
2016/0261258 Three Input Comparator
A three input voltage comparator provides termination of a pulse width modulation (PWM) output in a switched mode power supply. Shutdown of the PWM signal...
2016/0261257 Timing Prediction Circuit and Method
A timing prediction circuit and method which relate to the field of circuit technologies and may be used to predict a timing margin of a to-be-predicted...
2016/0261256 CLOCK TRANSMISSION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT
A clock transmission circuit includes a first buffer, a second buffer, and an inductor unit. The first buffer is configured to receive a first clock which is...
2016/0261255 ACCURATELY DETECTING LOW CURRENT THRESHOLD
A threshold detection circuit may sense when current between a power supply and a load reaches a current threshold level. The threshold detection circuit may...
2016/0261254 COMPENSATION CIRCUIT FOR OFFSET VOLTAGE IN A MEASUREMENT AMPLIFIER AND/OR FOR DC-SIGNAL COMPONENT IN A...
A circuit for the compensation of an offset voltage in a measurement amplifier and/or of a DC-signal component contained in a measurement signal is provided....
2016/0261253 COMPARISON CIRCUIT AND SENSOR DEVICE
To provide a comparison circuit capable of removing the influence of an offset voltage of a comparator in the comparison circuit and obtaining a highly...
2016/0261252 COMMON N-WELL STATE RETENTION FLIP-FLOP
Embodiments include apparatuses, methods, and systems for state retention electronic devices. In embodiments, an electronic device may include a state...
2016/0261251 DYNAMIC CLOCK RATE CONTROL FOR POWER REDUCTION
A pipeline system may adjust clock rates of variable-rate clock signals sent to different processing circuit blocks in a pipeline based on their respective,...
2016/0261250 Digital Filter With Confidence Input
A finite impulse response (FIR) digital filter has an assigned filter function with assigned filter coefficients, an input receiving input samples, another...
2016/0261249 SPLITTER
In a splitter, a first duplexer including a first transmit filter and a first receive filter at a first antenna terminal and a second duplexer including a...
2016/0261248 SURFACE ELASTIC WAVE DEVICE COMPRISING A SINGLE-CRYSTAL PIEZOELECTRIC FILM AND A CRYSTALLINE SUBSTRATE WITH LOW...
A surface elastic wave device comprises a stack including: a thin film made of a piezoelectric first material; a substrate made from a second material; and...
2016/0261247 ENHANCING AUDIO USING A MOBILE DEVICE
Embodiments disclosed herein enable detection and improvement of the quality of the audio signal using a mobile device by determining the loss in the audio...
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