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Patent # Description
2016/0268434 SOURCE/DRAIN REGIONS FOR FIN FIELD EFFECT TRANSISTORS AND METHODS OF FORMING SAME
A method for forming a semiconductor device includes forming a fin extending upwards from a semiconductor substrate and forming a sacrificial layer on...
2016/0268433 METHOD OF MAKING A CMOS SEMICONDUCTOR DEVICE USING A STRESSED SILICON-ON-INSULATOR (SOI) WAFER
A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer...
2016/0268432 SEMICONDUCTOR DEVICE
According to one embodiment, a semiconductor device includes a semiconductor substrate having a trench and including an active area including a channel area...
2016/0268431 FULLY DEPLETED DEVICE WITH BURIED INSULATING LAYER IN CHANNEL REGION
A semiconductor device includes an active region formed in a semiconductor substrate, a gate structure disposed over the active region, source/drain regions...
2016/0268430 METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURES INCLUDING FIN STRUCTURES WITH DIFFERENT STRAIN STATES, AND...
Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary...
2016/0268429 FinFET with Multiple Dislocation Planes and Method for Forming the Same
A method comprises forming a first fin and a second fin over a substrate, wherein the first fin and the second fin are separated by a trench, applying a first...
2016/0268428 ELECTRONIC DEVICE WITH ASYMMETRIC GATE STRAIN
The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and...
2016/0268427 Method for Inducing Strain in Vertical Semiconductor Columns
A vertical Metal-Oxide-Semiconductor (MOS) transistor includes a substrate and a nano-wire over the substrate. The nano-wire comprises a semiconductor...
2016/0268426 THREE-DIMENSIONAL TRANSISTOR WITH IMPROVED CHANNEL MOBILITY
A semiconductor device includes a plurality of spaced apart fins, a dielectric material layer positioned between each of the plurality of spaced apart fins,...
2016/0268425 Semiconductor Device Having a Fin at a Side of a Semiconductor Body
One embodiment of a semiconductor device includes a fin at a first side of a semiconductor body, a body region of a second conductivity type in at least a part...
2016/0268424 SEMICONDUCTOR STRUCTURE INCLUDING BACKGATE REGIONS AND METHOD FOR THE FORMATION THEREOF
A semiconductor structure includes a semiconductor substrate, a plurality of transistors and an electrically insulating layer provided between the substrate...
2016/0268423 Semiconductor Device, Integrated Circuit and Method of Manufacturing a Semiconductor Device
A semiconductor device includes a transistor in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region,...
2016/0268422 Method of Manufacturing a Semiconductor Device
A method of manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate of a first conductivity type having...
2016/0268421 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a first region of a first...
2016/0268420 SEMICONDUCTOR DEVICE
A semiconductor device is provided including a first electrode and a first semiconductor layer of a first conductivity type connected to the first electrode....
2016/0268419 SEMICONDUCTOR DEVICE
A semiconductor device includes a first semiconductor region of a first conductivity type, a first electrode, a second electrode, a third electrode, a first...
2016/0268418 NONVOLATILE MEMORY TRANSISTOR AND DEVICE INCLUDING THE SAME
Provided are nonvolatile memory transistors and devices including the nonvolatile memory transistors. A nonvolatile memory transistor may include a channel...
2016/0268417 DISPLAY DEVICE
According to one embodiment, a thin-film transistor includes a semiconductor layer SC including a channel region, and a source region and a drain region on...
2016/0268416 METHODS OF FORMING SEMICONDUCTOR DEVICES, INCLUDING FORMING A SEMICONDUCTOR MATERIAL ON A FIN, AND RELATED...
Methods of forming a semiconductor device are provided. A method of forming a semiconductor device includes forming a semiconductor layer on a fin, where the...
2016/0268415 GATE AND SOURCE/DRAIN CONTACT STRUCTURES FOR A SEMICONDUCTOR DEVICE
One illustrative device disclosed herein includes, among other things, a dielectric layer disposed above a source/drain region and a gate structure of a...
2016/0268414 Semiconductor Devices Including Insulating Gates and Methods for Fabricating the Same
Semiconductor devices are provided including a first active fin extending in a first direction and a second active fin spaced apart from the first active fin...
2016/0268413 DIAMOND SHAPED SOURCE DRAIN EPITAXY WITH UNDERLYING BUFFER LAYER
A semiconductor structure includes a fin upon a semiconductor substrate. A clean epitaxial growth surface is provided by forming a buffer layer upon fin...
2016/0268412 SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS
A semiconductor apparatus includes a substrate, a semiconductor layer formed above the substrate and including a nitride semiconductor, an electrode formed...
2016/0268411 HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) AND METHOD OF PRODUCING THE SAME
A high electron mobility transistor (HEMT) primarily made of nitride semiconductor materials is disclosed. The HEMT includes, on a substrate, a buffer layer, a...
2016/0268410 SEMICONDUCTOR DEVICE
A semiconductor device includes: a substrate; a first compound semiconductor layer provided on the substrate; a second compound semiconductor layer provided on...
2016/0268409 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer located on the first nitride semiconductor layer, a...
2016/0268408 SEMICONDUCTOR DEVICE
A semiconductor device includes a first compound semiconductor layer on a substrate, a second compound semiconductor layer on the first compound semiconductor...
2016/0268407 TECHNIQUES FOR FORMING CONTACTS TO QUANTUM WELL TRANSISTORS
Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used,...
2016/0268406 SINGLE-ELECTRON TRANSISTOR AND ITS FABRICATION METHOD
Single-electron transistor comprising at least: first semiconductor portions forming source and drain regions, a second semiconductor portion forming at...
2016/0268405 Thin-Substrate Double-Base High-Voltage Bipolar Transistors
B-TRAN bipolar power transistor devices and methods, using a drift region which is much thinner than previously proposed double-base bipolar transistors of...
2016/0268404 DUAL TRENCH-GATE IGBT STRUCTURE
An IGBT device includes a substrate having a bottom semiconductor layer of a first conductivity type and an upper semiconductor layer of a second conductivity...
2016/0268403 SEMICONDUCTOR DEVICE HAVING METAL LAYER AND METHOD OF FABRICATING SAME
A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and formed in the...
2016/0268402 METHOD FOR MANUFACTURING A TRANSISTOR
A method comprises arranging a stack, on a semiconductor substrate, comprising a sacrificial layer and an insulating layer. The insulator layer is at least...
2016/0268401 COMPLEMENTARY TUNNELING FET DEVICES AND METHOD FOR FORMING THE SAME
Described is an apparatus forming complementary tunneling field effect transistors (TFETs) using oxide and/or organic semiconductor material. One type of TFET...
2016/0268400 COMMON FABRICATION OF MULTIPLE FINFETs WITH DIFFERENT CHANNEL HEIGHTS
Commonly fabricated FinFET type semiconductor devices with different (i.e., both taller and shorter) heights of an entirety of or only the channel region of...
2016/0268399 METHODS OF FORMING EMBEDDED SOURCE/DRAIN REGIONS ON FINFET DEVICES
One illustrative method disclosed herein includes, among other things, forming a layer of insulating material in the source/drain regions of the device,...
2016/0268398 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
According to one embodiment, a method of manufacturing a semiconductor device comprises forming a semiconductor layer on a substrate, forming a first...
2016/0268397 Method of Manufacturing a Semiconductor Device
A method of manufacturing a semiconductor device includes forming a transistor in a semiconductor substrate having a first main surface. The transistor is...
2016/0268396 MANUFACTURING METHOD FOR VERTICAL CHANNEL GATE-ALL-AROUND MOSFET BY EPITAXY PROCESSES
A manufacturing method is provided for fabricating a vertical channel gate-all-around MOSFET by epitaxy processes. The method includes growing a first...
2016/0268395 SELF-ALIGNED SOURCE AND DRAIN REGIONS FOR SEMICONDUCTOR DEVICES
A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate...
2016/0268394 SEMICONDUCTOR DEVICE HAVING FIN-TYPE FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a substrate having a first region and a second region, a first MOS transistor including a first fin structure and a first gate...
2016/0268393 SEMICONDUCTOR DEVICES HAVING 3D CHANNELS, AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING 3D CHANNELS
A semiconductor device includes a substrate including first to third fins aligned in a first direction, a first trench arranged between the first fin and the...
2016/0268392 SEMICONDUCTOR ARRANGEMENT AND METHOD FOR MANUFACTURING THE SAME
A semiconductor arrangement and a method for manufacturing the same. An arrangement may include a bulk semiconductor substrate; a fin formed on the substrate;...
2016/0268391 METHODS FOR FORMING METAL SILICIDE
A method for forming a metal silicide. The method comprises: providing a substrate having a fin, a gate formed on the fin, and spacers formed on opposite sides...
2016/0268390 ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE
An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes...
2016/0268389 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor layer, a first electrode located over the semiconductor layer and connected to the semiconductor layer, a...
2016/0268388 NON-VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
A non-volatile memory device includes a semiconductor body extending in a first direction, an electrode extending in a second direction crossing the first...
2016/0268387 SPLIT-GATE FLASH MEMORY WITH IMPROVED PROGRAM EFFICIENCY
A split gate memory cell is fabricated with a word gate extending below an upper surface of a substrate having the channel region. An embodiment includes...
2016/0268386 Field Effect Power Transistor Metalization Having a Comb Structure with Contact Fingers
A metalization of a field effect power transistor having lateral semiconductor layers on an insulator substrate or an intrinsically conducting or doped...
2016/0268385 CLOSED CELL CONFIGURATION TO INCREASE CHANNEL DENSITY FOR SUB-MICRON PLANAR SEMICONDUCTOR POWER DEVICE
A semiconductor power device supported on a semiconductor substrate that includes a plurality of transistor cells, each cell has a source and a drain region...
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