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Patent # Description
2016/0267034 CONTROLLER, BUS CIRCUIT, CONTROL METHOD, AND RECORDING MEDIUM
A controller includes a pseudo device circuit connected to a target device with a bus and a reset line, the pseudo device circuit acquiring from the bus an...
2016/0267033 RESOLVING CONTENTION BETWEEN DATA BURSTS
In an embedded system, there are a plurality of data requesting devices, a plurality of data sources and a bus fabric interconnecting the data requesting...
2016/0267032 Processing Signals in a Quantum Computing System
In some aspects, a quantum computing system includes a control system and a quantum processor cell. The control system generates quantum processor control...
2016/0267031 DATA PROCESSOR AND CONTROL SYSTEM
Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller...
2016/0267030 INTEGRATED-CIRCUIT RADIO
An integrated-circuit radio communication device (1) comprises a processor (7) having a hardware-interrupt input line; memory (13); radio communication logic...
2016/0267029 SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREOF
According to one aspect, a module 11_1 includes a communication circuit 111 that performs data communication with an externally-provided control device 12...
2016/0267028 IDENTIFICATION OF MODULES ON A BUS
A method is provided for use in a host module, for identifying at least one accessory module on a bus, wherein the bus is configured to allow multiple...
2016/0267027 MEMORY DEVICE FOR COMPUTER
According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data....
2016/0267026 METHOD AND APPARATUS FOR ACCESSING PHYSICAL RESOURCES
A method and an apparatus for accessing physical resources, is used to restrict access to physical resources of other light system kernel Light OSs by a first...
2016/0267025 PRIVILEGE BASED MEMORY PINNING MECHANISM
A method for privilege based memory pinning is provided. The method includes receiving a request to pin an amount of address space memory from a process...
2016/0267024 Integrity Protection for Data Storage
A method and system for protecting the integrity of a memory system. An age counter and an opportunity counter are provided for each of multiple memory blocks....
2016/0267023 DATA MANAGEMENT METHOD, INFORMATION PROCESSING SYSTEM, AND TERMINAL DEVICE
A data management method includes receiving, by a terminal device, data stored in a first storage provided in an information processing device and storing the...
2016/0267022 ENCRYPTED DATA STORAGE AND RETRIEVAL SYSTEM
According to one embodiment, a system includes one or more memory units and one or more processors. The processors are configured to receive a plurality of...
2016/0267021 Managing Storage Block of a Data Volume
A mechanism for managing storage block of a data volume is disclosed. A method includes determining, by a processing device, whether a current data is to be...
2016/0267020 COMPUTING METHOD AND APPARATUS ASSOCIATED WITH CONTEXT-AWARE MANAGEMENT OF A FILE CACHE
Computer-readable storage media, computing devices and methods associated with file cache management are discussed herein. In embodiments, a computing device...
2016/0267019 GROUPING TRACKS FOR DESTAGING
Various embodiments for grouping tracks for destaging by a processor device in a computing environment are provided. Tracks are selected for destaging from a...
2016/0267018 PROCESSING DEVICE AND CONTROL METHOD FOR PROCESSING DEVICE
A processing device includes a processing unit that executes a memory access instruction, a cache memory, and a cache control unit. The cache control unit...
2016/0267017 DYNAMIC ADDRESS TRANSLATION WITH FETCH PROTECTION IN AN EMULATED ENVIRONMENT
What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial...
2016/0267016 STORAGE DEVICE, A HOST SYSTEM INCLUDING THE STORAGE DEVICE, AND A MAP TABLE UPDATING METHOD OF THE HOST SYSTEM
A host system includes a host device, a host buffer memory, and storage device. The host device includes a plurality of cores. The host buffer memory is...
2016/0267015 MAPPING VIRTUAL MEMORY PAGES TO PHYSICAL MEMORY PAGES
A method for mapping virtual memory pages to physical memory pages is described. The method includes receiving a mapping of a virtual memory page to multiple...
2016/0267014 STORAGE APPARATUS, STORAGE APPARATUS CONTROL METHOD, AND INFORMATION PROCESSING SYSTEM
A storage apparatus includes a physical memory including a plurality of first memory lines a part of which are assigned consecutive addresses and the rest of...
2016/0267013 TECHNIQUES TO PRELINK SOFTWARE TO IMPROVE MEMORY DE-DUPLICATION IN A VIRTUAL SYSTEM
Techniques to prelink software to improve memory de-duplication in a virtual system are described. An apparatus may comprise a processor circuit, a memory unit...
2016/0267012 STORAGE DEVICE AND MEMORY SYSTEM
According to one embodiment, a storage device includes a storage portion storing a first entry, the first entry includes a first translation table ...
2016/0267011 TAIL RESPONSE TIME REDUCTION METHOD FOR SSD
A Solid State Drive (SSD) is disclosed. The SSD can include a host interface logic, a data input buffer, a data output buffer, and a buffer manager to manage...
2016/0267010 MEMORY ACCESS CONTROL DEVICE, CACHE MEMORY AND SEMICONDUCTOR DEVICE
A memory access control device of an embodiment includes a data memory configured to record information of an access request relating to reading and writing of...
2016/0267009 METHOD AND APPARATUS FOR MEMORY ALIASING DETECTION IN AN OUT-OF-ORDER INSTRUCTION EXECUTION PLATFORM
A processor and method are described for alias detection. For example, one embodiment of an apparatus comprises: reordering logic to receive a set of read and...
2016/0267008 MEMORY SYSTEM
A memory system has a first cache memory comprising a volatile memory, a second cache memory comprising a non-volatile memory with access speed slower than...
2016/0267007 COMPUTING SYSTEM WITH ADAPTIVE BACK-UP MECHANISM AND METHOD OF OPERATION THEREOF
A computing system includes: an adaptive back-up controller configured to calculate an adaptive back-up time based on a reserve power source for backing up a...
2016/0267006 MASSIVE ACCESS REQUEST FOR OUT-OF-CORE TEXTURES BY A PARALLEL PROCESSOR WITH LIMITED MEMORY
In one embodiment, a method comprising organizing access request by a processor to elements of textures, wherein a storage representation of a plurality of all...
2016/0267005 MEMORY RECLAMATION ON A COMPUTING DEVICE
Various embodiments include methods for reclaiming memory in a computing device that may include storing a first pointer pointing to a first memory location...
2016/0267004 STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE AND GARBAGE COLLECTION METHOD THEREOF
A storage device is provided as follows. A nonvolatile memory device includes blocks, each block having sub-blocks erased independently. A memory controller...
2016/0267003 METHOD FOR CONTROLLING NONVOLATILE MEMORY AND STORAGE MEDIUM STORING PROGRAM
According to one embodiment, a method for controlling a nonvolatile memory includes allocating a first system block to a physical block included in one of the...
2016/0267002 STORAGE SYSTEM
According to one embodiment, a storage system includes a first storage and a controller which controls the first storage. The first storage includes a first...
2016/0267001 MONITORING DEVICE WITH FUNCTION OF EXTRACTING AND DISPLAYING BRANCH CIRCUIT IN LADDER PROGRAM
When a monitoring device for ladder program receives designation of a ladder program which is a confirmation object from a user, the monitoring device detects...
2016/0267000 TRANSACTIONAL EXECUTION OF NATIVE METHODS
Approaches for more efficiently executing calls to native code from within a managed execution environment are described. The techniques involve attempting to...
2016/0266999 GENERATION OF AUTOMATED UNIT TESTS FOR A CONTROLLER LAYER SYSTEM AND METHOD
A method, computer program product, and computer system for receiving, by a computing device, a selection of one or more files for which to have one or more...
2016/0266998 ERROR LIST AND BUG REPORT ANALYSIS FOR CONFIGURING AN APPLICATION TRACER
Error logs, bug reports, and other databases identifying problems with a tracer system may be mined to determine how a tracer may interact with a given...
2016/0266997 DEBUGGING CODE FOR CONTROLLING INTELLIGENT DEVICES USING LOG DATA FROM EXECUTED OBJECT CODE
In some aspects, a debugging application can obtain log data from a target device. The log data can be generated from the execution of object code by the...
2016/0266996 PROGRAM SUBSET EXECUTION AND DEBUG
A debugging module determines by analysis of code build information of a system with an identified error, where to set a debug entry point at which to start...
2016/0266995 DETECTING UNINITIALIZED MEMORY REFERENCES
A pre-initialized value of contents of a memory location is identified. A load value of contents loaded from the memory location by execution of a first...
2016/0266994 SYSTEM AND METHOD FOR USING DEVELOPMENT OBJECTIVES TO GUIDE IMPLEMENTATION OF SOURCE CODE
An information processing system, computer readable storage medium, and method with an integrated development environment to guide development of applications...
2016/0266993 VALIDATING CONNECTION, STRUCTURAL CHARACTERISTICS AND POSITIONING OF CABLE CONNECTORS
In one or more aspects, a determination is made as to whether a connector is securely fastened, whether the connector connected within a socket structure is...
2016/0266992 Instruction and logic to test transactional execution status
Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to...
2016/0266991 PREVENTING NON-DETECTABLE DATA LOSS DURING SITE SWITCHOVER
Methods, systems, and computer program products for preventing non-detectable data loss during site switchover are disclosed. A computer-implemented method may...
2016/0266990 OPTIMIZING DISASTER RECOVERY SYSTEMS DURING TAKEOVER OPERATIONS
Exemplary embodiments for optimizing disaster recovery systems during takeover operations are provided. In one embodiment, by way of example only, a flag is...
2016/0266989 INTERCONNECT PATH FAILOVER
One or more techniques and/or systems are provided for interconnect failover between a primary storage controller and a secondary storage controller. The...
2016/0266988 Data Processing Method, Device, and System for Storage Unit
A data processing method, a device, and a system for a storage unit in order to avoid performing repeated data read operations on the storage unit where the...
2016/0266987 SERVER SYSTEM, COMPUTER SYSTEM, METHOD FOR MANAGING SERVER SYSTEM, AND COMPUTER-READABLE STORAGE MEDIUM
In a server system, a hardware configuration comparison is made with respect to each combination of a current server and a backup server, and, by referring to...
2016/0266986 TEMPORARY PIPELINE MARKING FOR PROCESSOR ERROR WORKAROUNDS
Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring a pipeline of a processor for an...
2016/0266985 METHOD, INFORMATION PROCESSING APPARATUS, AND COMPUTER READABLE MEDIUM
A method includes: causing at least three processors to perform a same process; extracting, when one of the at least three processors outputs different...
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