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METHOD FOR THE FORMATION OF A FINFET DEVICE HAVING A PARTIALLY DIELECTRIC
ISOLATED FIN STRUCTURE
A semiconductor material is patterned to define elongated fins insulated from an underlying substrate. A polysilicon semiconductor material is deposited over...
SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE
To provide a semiconductor device with excellent electrical characteristics or a semiconductor device with stable electrical characteristics. A semiconductor...
CONDUCTIVE STRUCTURE AND METHOD OF MANUFACTURING THE SAME, ARRAY SUBSTRATE
The present invention discloses a conductive structure, a method of manufacturing the conductive structure, and an array substrate. The method of manufacturing...
Thin-Film Transistor Array Substrate And Method For Manufacturing
Thin-Film Transistor Array Substrate
A TFT array substrate and a method for manufacturing a TFT are disclosed. The TFT array substrate includes: a plurality of first metal lines, a first gap being...
ARRAY STRUCTURE, MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY
An array structure and a manufacturing method thereof are disclosed. The method for manufacturing the array structure includes: forming a gate insulating layer...
A semiconductor device includes a first pillar-shaped semiconductor layer, a first selection gate insulating film, a first selection gate, a first gate...
THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING
A semiconductor memory device includes a stack including gate electrodes sequentially stacked on a substrate, a vertical insulating structure penetrating the...
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
According to an embodiment, a semiconductor memory device comprises: a memory string comprising memory cells; and a contact electrically connected to one end...
METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a mask layer on the stacked body. The method includes...
SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device according to an embodiment comprises: a memory cell array, the memory cell array including: a conductive layer, an inter-layer...
SEMICONDUCTOR MEMORY DEVICE WITH FIRST AND SECOND SEMICONDUTOR FILMS IN
FIRST AND SECOND COLUMNAR BODIES
A semiconductor memory device according to an embodiment comprises: conductive layers stacked in a vertical direction on a semiconductor substrate; and first...
HONEYCOMB CELL STRUCTURE THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE
A monolithic three-dimensional memory device includes a plurality of memory stack structures arranged in a hexagonal lattice and located over a substrate. The...
METALLIC ETCH STOP LAYER IN A THREE-DIMENSIONAL MEMORY STRUCTURE
A dielectric liner, a bottom conductive layer, and a stack of alternating layers including insulator layers and spacer material layers are sequentially formed...
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
The present invention discloses a semiconductor device and a method for manufacturing the same, and the semiconductor device includes: a first area in which a...
Split Gate Non-volatile Memory Cell With 3D FINFET Structure, And Method
Of Making Same
A non-volatile memory cell including a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain...
SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device of the embodiments includes a first conductivity type semiconductor layer extending in a first direction and including a...
METHOD OF MAKING A PROGRAMMABLE CELL AND STRUCTURE THEREOF
A programmable cell includes a split gate structure. The split gate structure includes a thin gate dielectric region and a thick gate dielectric region...
SALICIDED STRUCTURE TO INTEGRATE A FLASH MEMORY DEVICE WITH A HIGH K,
METAL GATE LOGIC DEVICE
An integrated circuit for an embedded flash memory device is provided. A semiconductor substrate includes a memory region and a logic region adjacent to the...
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
A stacked body is disposed so as cover a periphery of a semiconductor columnar portion and includes a conductive layer and an inter-layer insulating layer...
SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL ARRAY AND POWER SUPPLY REGION
A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a...
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor device includes a first region having a first conductivity type in a semiconductor region; a second region having...
MERGED N/P TYPE TRANSISTOR
A semiconductor structure includes a semiconductor substrate, at least one first elongated region of n-type or p-type, and at least one other second elongated...
SEMICONDUCTOR DEVICES HAVING BIT LINES AND METHOD OF FABRICATING THE SAME
Semiconductor devices and methods of forming the semiconductor devices are provided. The semiconductor devices may include a bit line provided to cross an...
FINFET INCLUDING TUNABLE FIN HEIGHT AND TUNABLE FIN WIDTH RATIO
A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis...
DUAL STRAINED CLADDING LAYERS FOR SEMICONDUCTOR DEVICES
Techniques and methods related to dual strained cladding layers for semiconductor devices, and systems incorporating such semiconductor devices.
PLANAR DEVICE ON FIN-BASED TRANSISTOR ARCHITECTURE
Techniques are disclosed for forming a planar-like transistor device on a fin-based field-effect transistor (finFET) architecture during a finFET fabrication...
ELIMINATING FIELD OXIDE LOSS PRIOR TO FINFET SOURCE/DRAIN EPITAXIAL GROWTH
Method for forming FinFET source/drain regions with reduced field oxide loss and the resulting devices are disclosed. Embodiments include forming silicon fins...
Semiconductor Devices Having FIN Active Regions
Semiconductor devices are providing including a first isolation region configured to define a first fin active region protruding from a substrate, first gate...
Field-Effect Transistors Having Transition Metal Dichalcogenide Channels
and Methods of Manufacture
A transistor that is formed with a transition metal dichalcogenide material is provided. The transition metal dichalcogenide material is formed using a direct...
SEMICONDUCTOR DEVICES INCLUDING SHALLOW TRENCH ISOLATION (STI) LINERS
Semiconductor devices including STI liners are provided. The semiconductor devices may include a STI trench that defines an active region in a substrate, a STI...
A semiconductor device is provided. The semiconductor device may include a field insulating film on a substrate, a first fin type pattern which is formed on...
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a substrate, a first gate, a second gate, and an insulating structure. The substrate includes a first fin and a second fin. The...
Combination Metal Oxide Semi-Conductor Field Effect Transistor (MOSFET)
and Junction Field Effect Transistor...
Systems and methods for controlling current or mitigating electromagnetic or radiation interference effects using a combination of a metal-oxide semiconductor...
INTEGRATED CIRCUITS AND FABRICATION METHODS THEREOF
An integrated circuit includes a first polysilicon region having a first grain size formed on a substrate. The integrated circuit also includes a second...
MONOLITHIC MICROWAVE INTEGRATED CIRCUIT (MMIC) CASCODE CONNECTED
A cascode transistor circuit having an active region, the active region having a source, a drain, a floating source/drain, a first gate disposed between the...
TRANSISTORS PATTERNED WITH ELECTROSTATIC DISCHARGE PROTECTION AND METHODS
High-voltage semiconductor devices with electrostatic discharge (ESD) protection and methods of fabrication are provided. The semiconductor devices include a...
ELECTROSTATIC DISCHARGE PROTECTION DEVICE STRUCTURES AND METHODS OF
An ESD protection device comprising an SCR -type circuit including a PNP transistor and NPN transistor incorporates a Zener diode which permits the circuit to...
High Voltage ESD Protection Apparatus
A device comprises a high voltage n well and a high voltage p well over a buried layer, a first low voltage n well over the high voltage n well, wherein a...
SEMICONDUCTOR DEVICE AND METHOD FOR TESTING THE SEMICONDUCTOR DEVICE
A semiconductor device and a method for testing the semiconductor device are provided. The semiconductor device includes a diode (protection element) and a...
ESD PROTECTION STRUCTURE AND METHOD OF FABRICATION THEREOF
An ESD protection structure formed within an isolation trench and comprising a first peripheral semiconductor region of a first doping type, a second...
STRAPPING STRUCTURE OF MEMORY CIRCUIT
A memory circuit includes a first memory cell and a second memory adjacent to the first memory cell. The first memory cell includes a first word line strapping...
OPTOELECTRONICS AND CMOS INTEGRATION ON GOI SUBSTRATE
A method of forming an optoelectronic device and a silicon device on a single chip. The method may include; forming a stack of layers on a substrate in a first...
OPTOELECTRONIC DEVICE COMPRISING A LIGHT-EMITTING DIODE
The invention relates to a method of manufacturing optoelectronic devices including light-emitting diodes, including the steps of: a) forming a first...
LIGHT-EMITTING DEVICE, DEVICE AND METHOD FOR ADJUSTING THE LIGHT EMISSION
OF A LIGHT-EMITTING DIODE
Light-emitting device (100) comprising: a light-emitting diode (102) comprising: an emitting layer comprising a ternary or quaternary semiconductor...
The invention provides a photocoupler package. The photocoupler package includes a light-emitting diode (LED) mounted on a first lead frame, electrically...
Micro Solar Cell Powered Micro LED Display
Micro LEDs may be placed on a substrate in regularly spaced rows with an empty row between at least two successive rows of micro LED. A micro solar cell may...
METHOD OF EMBEDDING WLCSP COMPONENTS IN E-WLB AND E-PLB
Embodiments of the invention include multi-die package and methods of making such multi-die packages. In an embodiment a mold layer has a first surface and a...
SEMICONDUCTOR PACKAGE ASSEMBLY
The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first...
LIGHT-EMITTING DEVICE AND DISPLAY DEVICE
Disclosed herein is a light-emitting device including a plurality of first light-emitting elements mounted in a matrix form on a common wiring board. Each of...
LIGHT-EMITTING UNIT AND MANUFACTURING METHOD OF LIGHT-EMITTING UNIT
A light transmissive first insulating film having light transmissive property to visible light, a second insulating film arranged opposite to the first...