Easy To Use Patents Search & Patent Lawyer Directory
At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.
Searching:
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| 2016/0276321 |
LIGHT-EMITTING DEVICE A light-emitting device according to an embodiment includes a light-emitting part and an external wiring. The light-emitting part includes: a pair of... |
| 2016/0276320 |
SEMICONDUCTOR LIGHT-EMITTING DEVICE AND THE MANUFACTURING METHOD THEREOF A semiconductor light-emitting device that includes a substrate, at least one light-emitting unit arranged on the substrate, a phosphor layer at least covering... |
| 2016/0276319 |
FLEXIBLE LIGHT EMITTING SEMICONDUCTOR DEVICE WITH LARGE AREA CONDUIT A flexible polymeric dielectric layer (12) having first and second major surfaces, the first major surface having a conductive layer (20) thereon, the... |
| 2016/0276318 |
Package of LED Chip and Manufacturing Method Thereof The present invention discloses a package of the LED chip and the related manufacturing method. The present invention is related to the LED package process.... |
| 2016/0276317 |
BUMPLESS BUILD-UP LAYER PACKAGE WITH PRE-STACKED MICROELECTRONIC DEVICES The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL)... |
| 2016/0276316 |
STUB MINIMIZATION FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS A microelectronic assembly (300) or system (1500) includes at least one microelectronic package (100) having a microelectronic element (130) mounted face up... |
| 2016/0276315 |
Three-Dimensional Chip Stack and Method of Forming the Same A three-dimensional chip stack includes a first chip bonded to a second chip to form an electrical interconnection therebetween. The bonded interconnection... |
| 2016/0276314 |
Cooling Channels in 3DIC Stacks An integrated circuit structure includes a die including a semiconductor substrate, dielectric layers over the semiconductor substrate, an interconnect... |
| 2016/0276313 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF A semiconductor device according to the present embodiment includes a semiconductor substrate, an insulating film and a conductive film. The insulating film is... |
| 2016/0276312 |
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME A semiconductor device includes a wiring substrate, a first semiconductor chip provided on the wiring substrate, a supporting member provided on the wiring... |
| 2016/0276311 |
INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first... |
| 2016/0276310 |
EDGE STRUCTURE FOR BACKGRINDING ASYMMETRICAL BONDED WAFER Semiconductor devices and methods of forming a semiconductor device are disclosed. The device includes a wafer with top and bottom surfaces. The wafer includes... |
| 2016/0276309 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various electronic... |
| 2016/0276308 |
THERMALLY ENHANCED PACKAGE-ON-PACKAGE STRUCTURE A semiconductor package comprises a bottom package and a top package. The bottom package comprises at least one bottom-package semiconductor device. The top... |
| 2016/0276307 |
Semiconductor Device and Method of Forming POP Semiconductor Device with
RDL Over Top Package A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a... |
| 2016/0276306 |
REDUCING DEFECTS IN WAFER LEVEL CHIP SCALE PACKAGE (WLCSP) DEVICES Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces... |
| 2016/0276305 |
WINDOW CLAMP A wire bonding machine window clamp assembly. The assembly includes a support plate adapted to support a leadframe strip. The assembly also includes a frame... |
| 2016/0276304 |
INTEGRATED CIRCUIT PACKAGE Integrated circuit package including an integrated circuit, external connection elements (3) connected to the integrated circuit, a package material (2)... |
| 2016/0276303 |
ELECTRONIC COMPONENT An electric component comprising a terminal electrode and a hot-melt polymer layer formed on the terminal electrode, wherein the hot-melt polymer layer... |
| 2016/0276302 |
POWER MODULE A power module is disclosed, including a power module substrate in which a circuit layer is arranged on one surface of an insulating layer; and a semiconductor... |
| 2016/0276301 |
WIRING SUBSTRATE AND ELECTRONIC COMPONENT DEVICE A wiring substrate includes a connection pad formed in the outermost wiring layer, a dummy pad formed in the outermost wiring layer, and a dummy wiring portion... |
| 2016/0276300 |
ELECTRONIC DEVICE, AND MANUFACTURING METHOD OF ELECTRONIC DEVICE An electronic device includes a drive substrate (a pressure chamber substrate and a vibration plate) including a piezoelectric element and electrode wirings... |
| 2016/0276299 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer located on the first semiconductor... |
| 2016/0276298 |
ARRAY SUBSTRATE AND FABRICATING METHOD THEREOF AS WELL AS DISPLAY DEVICE This disclosure relates to an array substrate and fabricating method thereof as well as a display device, the array substrate comprising: a plurality of... |
| 2016/0276297 |
Jog Design in Integrated Circuits A device includes an active region in a semiconductor substrate, a gate strip over and crossing the active region, and a jog over the active region and... |
| 2016/0276296 |
TUNABLE COMPOSITE INTERPOSER A composite interposer can include a substrate element and a support element. The substrate element can have first and second opposite surfaces defining a... |
| 2016/0276295 |
Packaging Devices and Methods of Manufacture Thereof Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a method of manufacturing a packaging device... |
| 2016/0276294 |
INTEGRATED CIRCUIT ASSEMBLIES WITH REINFORCEMENT FRAMES, AND METHODS OF
MANUFACTURE An assembly with modules (110, 1310) containing integrated circuits and attached to a wiring substrate (120) is reinforced by one or more reinforcement frames... |
| 2016/0276293 |
LIGHT-EMITTING DEVICE AND BACKLIGHT MODULE USING THE SAME A light-emitting device is provided. The light-emitting device includes a substrate having a long edge and a short edge, at least one electrode pad assembly,... |
| 2016/0276292 |
SEMICONDUCTOR CHIP A semiconductor chip includes: a body; holes disposed in a first surface of the body; and a warpage preventing member including filling members disposed in the... |
| 2016/0276291 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE According to one embodiment, a semiconductor device includes: a semiconductor substrate; and an insulating film provided above the semiconductor substrate. The... |
| 2016/0276290 |
SEMICONDUCTOR PACKAGE AND MOBILE DEVICE USING THE SAME According to an embodiment, a semiconductor package includes a semiconductor chip mounted on an interposer board, a encapsulant sealing the semiconductor chip,... |
| 2016/0276289 |
WAFER STRUCTURE FOR ELECTRONIC INTEGRATED CIRCUIT MANUFACTURING A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the... |
| 2016/0276288 |
SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE INCLUDING ELECTROMAGNETIC
WAVE SHIELD LAYER A semiconductor package is provided with an electromagnetic wave shielding layer, and a conductive ground layer connected thereto. For example, in certain... |
| 2016/0276287 |
SEMICONDUCTOR DEVICE A semiconductor device capable of achieving a reduction of noise is provided. For example, the semiconductor device includes a first region for forming a core... |
| 2016/0276286 |
CHIP PART AND METHOD OF MAKING THE SAME A chip part includes a substrate, an element formed on the substrate, and an electrode formed on the substrate. A recess and/or projection expressing... |
| 2016/0276285 |
Method for Forming Alignment Marks and Structure of Same A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are... |
| 2016/0276284 |
Eliminate Sawing-Induced Peeling Through Forming Trenches A package includes a device die, a molding material encircling the device die, wherein a top surface of the molding material is substantially level with a top... |
| 2016/0276283 |
SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF The disclosed subject matter provides a semiconductor structure and fabrication method thereof. In a semiconductor structure, a dielectric layer, a plurality... |
| 2016/0276282 |
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME A semiconductor device includes a semiconductor layer, a first insulating film provided on the semiconductor layer, a second insulating film provided on the... |
| 2016/0276281 |
MANUFACTURING METHOD OF WIRING STRUCTURE AND WIRING STRUCTURE A trench is formed in an insulating film, carbon is formed on the insulating film to fill an inside of the trench, a catalytic material is formed on the... |
| 2016/0276280 |
ULTRATHIN MULTILAYER METAL ALLOY LINER FOR NANO CU INTERCONNECTS Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper... |
| 2016/0276279 |
SEMICONDUCTOR DEVICE A semiconductor device includes a semiconductor chip, an electrically insulating element separated from the semiconductor chip by a space, and encapsulation... |
| 2016/0276278 |
Packaged Semiconductor Devices, Methods of Packaging Semiconductor
Devices, and PoP Devices Packaged semiconductor devices, methods of packaging semiconductor devices, and package-on-package (PoP) devices are disclosed. In some embodiments, a method... |
| 2016/0276277 |
SEMICONDUCTOR DEVICE AND WAFER LEVEL PACKAGE INCLUDING SUCH SEMICONDUCTOR
DEVICE An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to... |
| 2016/0276276 |
SEMICONDUCTOR DEVICE According to one embodiment, a semiconductor device includes a substrate; a first interconnect portion provided on the substrate and including a plurality of... |
| 2016/0276275 |
MIS (METAL-INSULATOR-SEMICONDUCTOR) CONTACT STRUCTURES FOR SEMICONDUCTOR
DEVICES An MIS contact structure comprises a layer of semiconductor material, a layer of insulating material having a contact opening formed therein, a layer of... |
| 2016/0276274 |
POWER AND GROUND ROUTING OF INTEGRATED CIRCUIT DEVICES WITH IMPROVED IR
DROP AND CHIP PERFORMANCE An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first... |
| 2016/0276273 |
SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME A method for fabricating a semiconductor device includes preparing a substrate which includes a memory cell region and a peripheral circuit region; forming a... |
| 2016/0276272 |
SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first dielectric layer over the substrate. The... |
File A Patent Application
- Protect your idea -- Don't let someone else file first. Learn more.
- 3 Easy Steps -- Complete Form, application Review, and File. See our process.
- Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.