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Patent # Description
2016/0284859 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device with low parasitic capacitance is provided. The semiconductor device includes a first oxide insulator, an oxide semiconductor, a second...
2016/0284858 SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE
To provide a miniaturized transistor having highly stable electrical characteristics. Furthermore, also in a semiconductor device including the transistor,...
2016/0284857 Transistor and Electronic Device
A semiconductor device with favorable electrical characteristics or a highly reliable semiconductor device is provided. The semiconductor device is a...
2016/0284856 SEMICONDUCTOR DEVICE
A semiconductor device including a miniaturized transistor is provided. The semiconductor device includes a first insulator, a second insulator, a...
2016/0284855 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A highly reliable semiconductor device including a transistor using an oxide semiconductor is provided. In a semiconductor device including a bottom-gate...
2016/0284854 SEMICONDUCTOR DEVICE AND DISPLAY DEVICE INCLUDING SEMICONDUCTOR DEVICE
A semiconductor device includes a transistor which includes a first gate electrode, a first insulating film, an oxide semiconductor film, source and drain...
2016/0284853 LOW CONTACT RESISTANCE THIN FILM TRANSISTOR
The present invention relates to a novel thin film transistor (TFT) comprising a substrate (100) with a gate electrode layer (101) deposited and patterned...
2016/0284852 GATE-ALL-AROUND FIN DEVICE
A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a...
2016/0284851 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a substrate, a semiconductor fin, a gate stack, and an epitaxy structure. The semiconductor fin is disposed in the substrate. A...
2016/0284850 FACETED FINFET
Among other things, a semiconductor device comprising one or more faceted surfaces and techniques for forming the semiconductor device are provided. A...
2016/0284849 Diode Structure Compatible with FinFET Process
An embodiment integrated circuit (e.g., diode) and method of making the same. The embodiment integrated circuit includes a well having a first doping type...
2016/0284848 FinFETs with Strained Well Regions
A device includes a substrate, insulation regions extending into the substrate, a first semiconductor region between the insulation regions and having a first...
2016/0284847 FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION
A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer...
2016/0284846 FORMING TUNNELING FIELD-EFFECT TRANSISTOR WITH STACKING FAULT AND RESULTING DEVICE
Devices including stacking faults in sources, or sources and drains, of TFETs are disclosed to improve tunneling efficiency. Embodiments may include a...
2016/0284845 INTEGRATED CIRCUITS AND METHODS OF FORMING INTEGRATED CIRCUITS
An integrated circuit includes a gate electrode and spacers along sidewalls of the gate electrode. The integrated circuit further includes a source/drain (S/D)...
2016/0284844 SEMICONDUCTOR DEVICE
A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate and that extends in a first direction with a first insulating...
2016/0284843 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
An object is to provide a technique that suppresses decrease in the breakdown voltage of a protective element. There is provided a semiconductor device that...
2016/0284842 Lateral MOSFET
A device includes a plurality of isolation regions formed in a substrate, wherein a top surface of a first isolation region is lower than a top surface of the...
2016/0284841 Composite Semiconductor Device with Different Channel Widths
A device includes a semiconductor substrate, a first constituent transistor including a first plurality of transistor structures in the semiconductor substrate...
2016/0284840 Method for Producing a Controllable Semiconductor Component Having Trenches with Different Widths and Depths
A controllable semiconductor component is produced by providing a semiconductor body with a top side and a bottom side, and forming a first trench protruding...
2016/0284839 MOSFET
In a plane view of the front surface of the semiconductor substrate, the source region and the first contact region are arranged adjacent to each other in a...
2016/0284838 TRENCH MOSFET SHIELD POLY CONTACT
A recess is formed at a semiconductor layer of a device to define a plurality of mesas. An active trench portion of the recess residing between adjacent mesas....
2016/0284837 SEMICONDUCTOR DEVICE HAVING STRESSOR AND METHOD OF FABRICATING THE SAME
A semiconductor device may include a fin active region including a lower fin region surrounded by a device isolation layer and an upper fin active region...
2016/0284836 SYSTEM, APPARATUS, AND METHOD FOR N/P TUNING IN A FIN-FET
The n-type to p-type fin-FET strength ratio in an integrated logic circuit may be tuned by the use of cut regions in the active and dummy gate electrodes. In...
2016/0284835 SEMICONDUCTOR DEVICE HAVING SUPER JUNCTION METAL OXIDE SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD FOR THE SAME
A semiconductor device includes: a first base layer; a drain layer disposed on the back side surface of the first base layer; a second base layer formed on the...
2016/0284834 SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVING DEVICE, VEHICLE, AND ELEVATOR
A semiconductor device according to the embodiments includes a SiC layer having a first plane, an insulating layer, and a region between the first plane and...
2016/0284833 SEMICONDUCTOR DEVICE AND INVERTER CIRCUIT
A semiconductor device according to embodiments includes a p-type SiC layer having a first plane, a gate electrode, and a gate insulating layer provided...
2016/0284832 GROUP III NITRIDE INTEGRATION WITH CMOS TECHNOLOGY
A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The...
2016/0284831 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device of an embodiment includes a first GaN-based semiconductor layer, a second GaN-based semiconductor layer provided on the first GaN-based...
2016/0284830 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device of an embodiment includes a first layer, a second layer provided on the first layer, the second layer forming a two-dimensional electron...
2016/0284829 FAULT TOLERANT DESIGN FOR LARGE AREA NITRIDE SEMICONDUCTOR DEVICES
A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor...
2016/0284828 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device of an embodiment includes a first layer, a second layer provided on the first layer, the second layer forming a two-dimensional electron...
2016/0284827 HIGH ELECTRON MOBILITY TRANSISTOR WITH INDIUM NITRIDE LAYER
A semiconductor device includes an indium gallium nitride layer over an active layer. The semiconductor device further includes an annealed region beneath the...
2016/0284826 BIPOLAR NON-PUNCH-THROUGH POWER SEMICONDUCTOR DEVICE
The invention relates to a bipolar non-punch-through power semiconductor device and a corresponding manufacturing method. The device comprises a semiconductor...
2016/0284825 SEMICONDUCTOR DEVICE
A semiconductor device of the present invention is structured such that in a surface layer of a first principal surface of a semiconductor substrate, an n-type...
2016/0284824 Semiconductor Device and Manufacturing Method Thereof
An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a first trench gate electrode and second and third...
2016/0284823 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A transistor with stable electrical characteristics is provided. Provided is a method for manufacturing a semiconductor device that includes, over a substrate,...
2016/0284822 METHOD FOR MAKING A SEMICONDUCTOR DEVICE WITH SIDEWAL SPACERS FOR CONFINIG EPITAXIAL GROWTH
A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is...
2016/0284821 NANOWIRE TRANSISTOR WITH UNDERLAYER ETCH STOPS
A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at...
2016/0284820 SYMMETRICAL EXTENSION JUNCTION FORMATION WITH LOW-K SPACER AND DUAL EPITAXIAL PROCESS IN FINFET DEVICE
A technique relates to a dual epitaxial process a device. A first spacer is disposed on a substrate, dummy gate, and hardmask. A first area extends in a first...
2016/0284819 THIN FILM TRANSISTOR, ITS MANUFACTURING METHOD AND DISPLAY DEVICE
The present disclosure relates to the field of display technology, and provides a TFT, its manufacturing method and a display device. A first region of an...
2016/0284818 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
A semiconductor device is disclosed. The semiconductor device comprising: a semiconductor substrate having first type conductivity and including an active...
2016/0284817 REPLACEMENT METAL GATE STRUCTURES
Replacement metal gate structures with improved chamfered workfunction metal and self-aligned contact and methods of manufacture are provided. The method...
2016/0284816 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a substrate, a channel layer, a spacer layer, a barrier layer, and an oxidized cap layer. The channel layer is disposed on or...
2016/0284815 GROUP-III NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
The present invention discloses a group-III nitride semiconductor device, which comprises a substrate, a buffer layer, a semiconductor stack structure, and a...
2016/0284814 SEMICONDUCTOR DEVICE METHOD
In one embodiment, an IGBT is formed to include a plurality of termination trenches in a termination region of the IGBT. An embodiment may include that one end...
2016/0284813 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device including a graphene layer and a method of manufacturing the same are disclosed. A method in which graphene is grown on a catalyst metal...
2016/0284812 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
There is provided a method of manufacturing a semiconductor device. The method of manufacturing comprises a film formation process of forming a molybdenum...
2016/0284811 ELECTRONICS INCLUDING GRAPHENE-BASED HYBRID STRUCTURES
Device are described that include a semiconductor material layer and at least one graphene-based electrode disposed over a portion of the semiconductor...
2016/0284810 TECHNIQUES FOR MULTIPLE GATE WORKFUNCTIONS FOR A NANOWIRE CMOS TECHNOLOGY
In one aspect, a method of forming a CMOS device with multiple transistors having different Vt's is provided which includes: forming nanowires and pads on a...
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