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Patent # Description
2016/0284759 SEMICONDUCTOR DEVICE
In a solid state image sensor which has two photodiodes juxtaposed in a predetermined direction in each pixel and is formed by carrying out divided exposure,...
2016/0284758 PHOTOELECTRIC CONVERSION APPARATUS AND CAMERA
A photoelectric conversion apparatus includes a charge accumulation region of a first conductivity type, a first semiconductor region of a second conductivity...
2016/0284757 IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME
An image sensor is provided. The sensor comprises a plurality of photoelectric conversion elements each including a charge accumulation region of a first...
2016/0284756 SOLID-STATE IMAGING APPARATUS
The present invention relates to a solid-state imaging apparatus including a first substrate having a plurality of photoelectric conversion units and a second...
2016/0284755 SEMICONDUCTOR APPARATUS
A semiconductor apparatus includes a conductive member penetrating through a first semiconductor layer, a first insulator layer, and a third insulator layer,...
2016/0284754 SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE, AND IMAGING APPARATUS
A semiconductor device includes a plurality of substrates including a semiconductor layer and a wiring layer, wherein each of the plurality of substrates is...
2016/0284753 SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS
A semiconductor device includes a first semiconductor substrate (12) in which a pixel region (21) where pixel portions (51) performing photoelectric conversion...
2016/0284752 METHODS OF FORMING INTEGRATED PACKAGE STRUCTURES WITH LOW Z HEIGHT 3D CAMERA
Methods of forming 3D camera devices and structures formed thereby are described. An embodiment includes a first optics module and a second optics module...
2016/0284751 CHIP SCALE SENSING CHIP PACKAGE AND A MANUFACTURING METHOD THEREOF
This present invention provides a chip scale sensing chip package, comprising a sensing chip having a first top surface and a first bottom surface opposite to...
2016/0284750 One Transistor Active Pixel Sensor with Tunnel FET
A tunneling field effect transistor for light detection, including a p-type region connected to a source terminal, a n-type region connected to a drain...
2016/0284749 IMAGING DEVICE AND ELECTRONIC DEVICE
An imaging device with excellent imaging performance is provided. The imaging device has a first circuit including a first photoelectric conversion element and...
2016/0284748 APPARATUS AND METHOD USING A DUAL GATE TFT STRUCTURE
A detector having an array of pixels arranged in columns and rows. Each of the pixels has a photosensor and a switch device. The switch devices in each pair of...
2016/0284747 4-COLOR IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME
A 4-color image sensor may include a first unit pixel region having Gr, R, IR and B pixels on four divided regions; and a second unit pixel region having IR,...
2016/0284746 SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME
According to one embodiment, a solid-state imaging device includes a plurality of photoelectric conversion elements, a field effect transistor, a trench, and a...
2016/0284745 IMAGE SENSOR CHIP
The present invention relates to an image sensor chip of which the efficiency such as sensitivity/quantum efficiency (QE) and the like can be improved by...
2016/0284744 PHOTODIODE ARRAY
A light receiving region includes a plurality of light detecting sections 10. The light detecting sections 10 has a second contact electrode 4A. The second...
2016/0284743 CIRCUIT AND METHOD FOR CONTROLLING A SPAD ARRAY
A circuit may include an array of single photon avalanche diode (SPAD) cells, each SPAD cell configured to be selectively enabled by an activation signal. The...
2016/0284742 FABRICATION METHOD OF ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY DEVICE
A fabrication method of an array substrate (10), an array substrate (10), and a display device are provided, the array substrate comprising a pixel region, an...
2016/0284741 ARRAY SUBSTRATE FABRICATING METHOD
The present invention provides an array substrate fabricating method. The array substrate fabricating method comprises the steps of: forming a semiconductor...
2016/0284740 Digital Circuit Having Correcting Circuit and Electronic Apparatus Thereof
Provided is a digital circuit (30) that comprises: a switching circuit (31) having first transistors (32, 33) supplied with power supply potentials (VDD, VSS);...
2016/0284739 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed...
2016/0284738 THIN FILM TRANSISTOR ARRAY PANEL AND DISPLAY DEVICE INCLUDING THE SAME
Embodiments of the present invention relate to a thin film transistor array panel and a display device including the same. An exemplary embodiment of the...
2016/0284737 DISPLAY SUBSTRATE, ITS MANUFACTURING METHOD, AND DISPLAY DEVICE
The present disclosure provides a display substrate, its manufacturing method and a display device. The display substrate includes a base substrate, and a film...
2016/0284736 ADJACENT STRAINED <100> NFET FINS AND <110> PFET FINS
The present invention relates generally to semiconductor devices, and more particularly, to a structure and method of forming strained <100> n-channel...
2016/0284735 LIQUID CRYSTAL DISPLAY DEVICE
A liquid crystal display device includes a TFT substrate having a display region with first and second electrodes, TFTs, scanning signal lines connected to the...
2016/0284734 THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF
A thin film transistor array panel includes a substrate, a first gate electrode disposed on the substrate, a voltage wire disposed on the substrate, a gate...
2016/0284733 METHOD OF MANUFACTURING DISPLAY APPARATUS AND DISPLAY APPARATUS MANUFACTURED THROUGH THE METHOD
A method of manufacturing a display apparatus includes: preparing a substrate including a pixel circuit region and a driving circuit region; forming a first...
2016/0284732 ARRAY SUBSTRATE AND METHODS OF MANUFACTURING AND DRIVING THE SAME
Embodiments of the present disclosure relate to the field of display technologies, and particularly, to an array substrate and methods of manufacturing and...
2016/0284731 EFFICIENT BURIED OXIDE LAYER INTERCONNECT SCHEME
An integrated circuit has a buried interconnect in the buried oxide layer connecting a body of a MOS transistor to a through-substrate via (TSV). The buried...
2016/0284730 NAND MEMORY STRINGS AND METHODS OF FABRICATION THEREOF
Methods of making monolithic three-dimensional memory devices include performing a first etch to form a memory opening and a second etch using a different...
2016/0284729 NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME
A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory...
2016/0284728 APPARATUSES AND METHODS FOR FORMING MULTIPLE DECKS OF MEMORY CELLS
Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck...
2016/0284727 SEMICONDUCTOR MEMORY DEVICE
According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation...
2016/0284726 MID-TUNNELING DIELECTRIC BAND GAP MODIFICATION FOR ENHANCED DATA RETENTION IN A THREE-DIMENSIONAL SEMICONDUCTOR...
A tunneling dielectric layer for a vertical memory device is formed with a stack that provides a barrier height profile for high data retention tolerance....
2016/0284725 METHOD OF FABRICATING THREE-DIMENSIONAL GATE-ALL-AROUND VERTICAL GATE STRUCTURES AND SEMICONDUCTOR DEVICES, AND...
Present example embodiments relate generally to methods of fabricating a three-dimensional gate-all-around (GAA) vertical gate (VG) semiconductor structure...
2016/0284724 Method Of Forming 3D Vertical NAND With III-V Channel
Disclosed herein is 3D memory with vertical NAND strings having a III-V compound channel, as well as methods of fabrication. The III-V compound has at least...
2016/0284723 3D Vertical NAND With III-V Channel
Disclosed herein is 3D memory with vertical NAND strings having a III-V compound channel, as well as methods of fabrication. The III-V compound has at least...
2016/0284722 MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME
A memory device including a substrate, at least one first stacked structure and at least one second stacked structure disposed on the substrate is provided....
2016/0284721 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device may include a substrate provided in a peripheral region, first and second insulation pillars formed in the substrate, and a gate...
2016/0284720 SEMICONDUCTOR DEVICE
There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores...
2016/0284719 Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells
Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive...
2016/0284718 Common Source Line with Discrete Contact Plugs
A method of forming a NAND flash memory includes forming a conductive area in a substrate, the conductive area extending along a direction that is...
2016/0284717 PILLAR ARRANGEMENT IN NAND MEMORY
Embodiments of the present disclosure are directed towards techniques and configurations for providing a 3D memory array apparatus. In one embodiment, the...
2016/0284716 FEED-FORWARD BIDIRECTIONAL IMPLANTED SPLIT-GATE FLASH MEMORY CELL
A split-gate flash memory cell (cell) includes a semiconductor surface. A first control gate (CG) on a first floating gate (FG) and a second CG on a second...
2016/0284715 PATTERNING FOR VARIABLE DEPTH STRUCTURES
A method of forming a NAND flash memory includes forming a dielectric layer over NAND strings separated by shallow trench isolation structures, forming an...
2016/0284714 USE OF AMBIENT-ROBUST SOLUTION PROCESSING FOR PREPARING NANOSCALE ORGANIC FERROELECTRIC FILMS
Disclosed is a method for preparing a ferroelectric film having ferroelectric hysteresis properties, the method comprising (a) obtaining a composition...
2016/0284713 SEMICONDUCTOR MEMORY DEVICE
The semiconductor memory device of the invention includes 2 TFT MOS transistors, 2 bulk MOS transistors, a first and second access MOS transistors and a first...
2016/0284712 DUAL-PORT SRAM CELL STRUCTURE WITH VERTICAL DEVICES
Dual-Port SRAM cells are described. In an embodiment, a cell includes first and second pull-down, first and second pull-up, and first through fourth pass-gate...
2016/0284711 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME
In a conventional DRAM, when the capacitance of a capacitor is reduced, an error of reading data easily occurs. A plurality of cells are connected to one bit...
2016/0284710 METHOD FOR FORMING BURIED BIT LINE, SEMICONDUCTOR DEVICE HAVING THE SAME, AND FABRICATING METHOD THEREOF
A method for fabricating a semiconductor device includes: etching a semiconductor substrate and forming a plurality of bodies separated from one another by a...
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