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Patent # Description
2016/0284609 DYNAMIC INTEGRATED CIRCUIT FABRICATION METHODS
Methods and processes for forming semiconductor devices with reduced yield loss and failed dies are provided. One method includes, for instance: obtaining a...
2016/0284608 METHOD FOR REDUCING THE METAL CONTAMINATION ON A SURFACE OF A SUBSTRATE
The present disclosure relates to a method for reducing metal contamination on a surface of a substrate. The method involves plasma treatment of the surface of...
2016/0284607 DUAL CHANNEL FINFET WITH RELAXED PFET REGION
Fabricating a semiconductor device includes providing a strained semiconductor material (SSM) layer disposed on a dielectric layer, forming a first plurality...
2016/0284606 SILICON-GERMANIUM FINFET DEVICE WITH CONTROLLED JUNCTION
Embodiments of the invention include a method for <something> and the resulting structure. A semiconductor device including a substrate, a ...
2016/0284605 Methods for Fabricating Strained Gate-All-Around Semiconductor Devices by Fin Oxidation Using an Undercut...
Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a...
2016/0284604 Techniques for Dual Dielectric Thickness for a Nanowire CMOS Technology Using Oxygen Growth
In one aspect, a method of forming a CMOS device includes forming nanowires suspended over a BOX, wherein a first/second one or more of the nanowires are...
2016/0284603 MULTI-LAYER SEMICONDUCTOR STRUCTURES FOR FABRICATING INVERTER CHAINS
Systems and methods are provided for fabricating a semiconductor structure including an inverter chain. An example semiconductor structure includes a first...
2016/0284602 MACRO TO MONITOR N-P BUMP
A technique relates to fabricating a macro for measurements utilized in dual spacer, dual epitaxial transistor devices. The macro is fabricated according to a...
2016/0284601 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES COMPRISING EPITAXIAL LAYERS
A method for manufacturing semiconductor devices includes following steps. A substrate including a first gate structure and a second gate structure formed...
2016/0284600 Memory Cell Layout
A system and method for a memory cell layout is disclosed. An embodiment comprises forming dummy layers and spacers along the sidewalls of the dummy layer....
2016/0284599 BURIED SOURCE-DRAIN CONTACT FOR INTEGRATED CIRCUIT TRANSISTOR DEVICES AND METHOD OF MAKING SAME
An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filled with a metal material to form a source (or...
2016/0284598 FIN END SPACER FOR PREVENTING MERGER OF RAISED ACTIVE REGIONS
After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a...
2016/0284597 Epitaxial Growth of Doped Film for Source and Drain Regions
Embodiments of mechanisms for epitaxially growing one or more doped silicon-containing materials to form source and drain regions of finFET devices are...
2016/0284596 PARTIALLY RECESSED CHANNEL CORE TRANSISTORS IN REPLACEMENT GATE FLOW
An integrated circuit containing MOS transistors with replacement gates may be formed with elevated LDD regions and/or recessed replacement gates on a portion...
2016/0284595 SELECTIVE ANALOG AND RADIO FREQUENCY PERFORMANCE MODIFICATION
A semiconductor chip includes a circuit block. The circuit block includes a first transistor(s) having an enhanced first performance characteristic different...
2016/0284594 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a plurality of fins on the semiconductor substrate;...
2016/0284593 AIR-GAP FORMING TECHNIQUES FOR INTERCONNECT STRUCTURES
The present disclosure relates to a method of forming an interconnect structure. In some embodiments, the method is performed by forming a trench within a...
2016/0284592 ADHESION LAYER FORMING METHOD, ADHESION LAYER FORMING SYSTEM AND RECORDING MEDIUM
An adhesion layer formed of a thin film can be formed on a surface of a substrate. An adhesion layer forming method of forming the adhesion layer on the...
2016/0284591 SELF-ALIGNED SEMICONDUCTOR FABRICATION WITH FOSSE FEATURES
The present disclosure describes methods for transferring a desired layout into a target layer on a semiconductor substrate. An embodiment of the methods...
2016/0284590 Method of Fabricating Semiconductor Device
A method for fabricating a semiconductor device includes forming a first material layer over a substrate, forming a middle layer over the first material layer,...
2016/0284589 Layer Transfer Technology for Silicon Carbide
Devices that include a layer of silicon carbide and methods for making such devices are disclosed. A method includes obtaining a first silicon carbide wafer...
2016/0284588 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD
A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is...
2016/0284587 SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF
A semiconductor process including the following step is provided. A sacrificial layer is formed in a substrate. The sacrificial layer and the substrate are...
2016/0284586 METHOD AND STRUCTURE TO SUPPRESS FINFET HEATING
Embodiments of the present invention provide structures and methods for heat suppression in finFET devices. Fins are formed in a semiconductor substrate. A...
2016/0284585 SUBSTRATE HOLDING METHOD AND SUBSTRATE PROCESSING APPARATUS
A substrate holding method is to horizontally hold a substrate, and includes a positioning step of positioning a substrate by moving a substrate transfer...
2016/0284584 SEMICONDUCTOR APPARATUS WITH TRANSPORTABLE EDGE RING FOR SUBSTRATE TRANSPORT
An apparatus and method for processing semiconductor substrates provides a substrate stage being a rotatable disc with a solid surface and a terraced edge with...
2016/0284583 THERMOPLASTIC TEMPORARY ADHESIVE FOR SILICON HANDLER WITH INFRA-RED LASER WAFER DE-BONDING
A bonding material including a phenoxy resin thermoplastic component, and a carbon black filler component. The carbon black filler component is present in an...
2016/0284582 THERMOPLASTIC TEMPORARY ADHESIVE FOR SILICON HANDLER WITH INFRA-RED LASER WAFER DE-BONDING
A bonding material including a phenoxy resin thermoplastic component, and a carbon black filler component. The carbon black filler component is present in an...
2016/0284581 Method of Manufacturing Semiconductor Device
Provided are a substrate processing apparatus, a method of processing a substrate, a method of manufacturing a semiconductor device, and a non-transitory...
2016/0284580 WAFER STORAGE CONTAINER
The present invention relates to a wafer storage container, more particularly, relates to a wafer storage container wherein the space of the wafer storage...
2016/0284579 PROCESS WINDOW ANALYSIS
A method for process analysis includes acquiring first inspection data, using a first inspection modality, with respect to a substrate having multiple...
2016/0284578 WAFER PROCESSING SYSTEMS INCLUDING MULTI-POSITION BATCH LOAD LOCK APPARATUS WITH TEMPERATURE CONTROL CAPABILITY
Various embodiments of wafer processing systems including batch load lock apparatus with temperature control capability are disclosed. The batch load lock...
2016/0284577 SUBSTRATE TRANSFER METHOD AND SUBSTRATE PROCESSING APPARATUS
A substrate transfer method of a substrate processing apparatus that includes a load lock chamber including a drive unit that is capable of forming, between a...
2016/0284576 RESIN SEALING APPARATUS AND RESIN SEALING METHOD
A lower mold has a bottom surface member and a side surface member. An upper end surface of the bottom surface member forms an inner bottom surface of a cavity...
2016/0284575 THERMAL PROCESSING METHOD AND THERMAL PROCESSING APPARATUS FOR HEATING SUBSTRATE, AND SUSCEPTOR
A semiconductor wafer with (100) plane orientation has two orthogonal cleavage directions. A notch is provided so as to indicate one of these directions....
2016/0284574 PURGING OF POROGEN FROM UV CURE CHAMBER
A purge ring for providing a gas to a wafer processing chamber includes an inlet ring wall defining a ring hole space. An outer perimeter of the inlet ring...
2016/0284573 LIGHT IRRADIATION TYPE HEAT TREATMENT APPARATUS AND METHOD FOR MANUFACTURING HEAT TREATMENT APPARATUS
A sealing structure is achieved by sandwiching an O ring between an upper chamber window and a chamber side portion and pressing a clamping ring against a top...
2016/0284572 HEATER BLOCK AND SUBSTRATE PROCESSING APPARATUS
Present disclosure relates to a heater block including a plurality of heating lamps mounted on one surface thereof facing an object to be processed, e.g., a...
2016/0284571 SUBSTRATE PROCESSING APPARATUS
The substrate processing apparatus includes a processing chamber including an outer chamber configured to hold a processing liquid and an inner chamber capable...
2016/0284570 ENCAPSULATED DIES WITH ENHANCED THERMAL PERFORMANCE
The present disclosure relates to a semiconductor package having encapsulated dies with enhanced thermal performance. The semiconductor package includes a...
2016/0284569 Apparatus and Method for Self-Aligning Chip Placement and Leveling
An approach is provided for aligning and leveling a chip package portion. The approach involves filling, at least partially, a reservoir formed between a first...
2016/0284568 ENCAPSULATED DIES WITH ENHANCED THERMAL PERFORMANCE
The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip...
2016/0284567 PULSED NITRIDE ENCAPSULATION
Aspects of the disclosure pertain to methods of forming conformal liners on patterned substrates having high height-to-width aspect ratio gaps. Layers formed...
2016/0284566 SEMICONDUCTOR DEVICE MOUNTING METHOD
A first insulating film is applied onto a joining face of a semiconductor device including a connection terminal on a joining face, and the connection terminal...
2016/0284565 SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A semiconductor device manufacturing method which enhances the reliability of the semiconductor device. The method uses a lead frame (hoop) which includes a...
2016/0284564 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
In a manufacturing process of a transistor including an oxide semiconductor film, oxygen doping treatment is performed on the oxide semiconductor film, and...
2016/0284563 SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME AND POWER CONVERTER
The method for manufacturing comprises an ion implantation process of implanting a p-type impurity into a semiconductor layer mainly made of a group III...
2016/0284562 APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING SAME
The present disclosure controls the heat source unit such that a to-be-processed object in which a hydrogen-containing to-be-processed layer is formed is...
2016/0284561 Method of Manufacturing a Semiconductor Device Having a Buried Channel/Body Zone
A method of manufacturing a semiconductor device includes etching cavities into a semiconductor layer by crystallographic etching having an etch rate that...
2016/0284560 PATTERN FORMING METHOD
A pattern forming method in an embodiment includes forming, on or above a substrate, a block copolymer layer containing a first polymer and a second polymer...
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