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Patent # Description
2016/0293740 MAGNETORESISTIVE ELEMENT, SPIN MOSFET, AND SPIN-TRANSPORT ELEMENT
The magnetoresistive element includes a semiconductor channel layer, a pinned layer disposed on the semiconductor channel layer via a first tunnel layer, a...
2016/0293739 VERTICAL GATE-ALL-AROUND TFET
A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET...
2016/0293738 METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE
An improvement is made in the reliability of a semiconductor device having a split gate type MONOS memory. An ONO film covering a control gate electrode, and a...
2016/0293737 DUAL WIDTH FINFET
A dual width SOI FinFET is disclosed in which different portions of a strained fin have different widths. A method of fabrication of such a dual width FinFET...
2016/0293736 DAMAGE-RESISTANT FIN STRUCTURES AND FINFET CMOS
A design structure for a semiconductor circuit structure, readable by a machine used in design, manufacture, or simulation of an integrated circuit, involves a...
2016/0293735 Semiconductor Device with Strained Layer
A semiconductor device and method of fabricating thereof is described that includes a substrate including at least one fin, at least one gate stack formed on a...
2016/0293734 FORMING PUNCH-THROUGH STOPPER REGIONS IN FINFET DEVICES
In forming a punch-through stopper region in a fin field effect transistor (finFET) device, a substrate may be etched to form a pair of trenches that define a...
2016/0293733 FORMING MULTI-STACK NANOWIRES USING A COMMON RELEASE MATERIAL
A method for forming a multi-stack nanowire device includes forming a common release layer on a substrate, the common release layer comprising a common release...
2016/0293732 Method for Manufacturing Semiconductor Device
A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A...
2016/0293731 REPLACEMENT METAL GATE DIELECTRIC CAP
A method for manufacturing a field effect transistor includes chelating a molecular mask to a replacement metal gate in a field effect transistor. The method...
2016/0293730 Structure and Method for a Field Effect Transistor
A method of forming a semiconductor structure includes forming a shallow trench isolation (STI) feature in a semiconductor substrate. An active region is...
2016/0293729 SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF
A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially...
2016/0293728 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES
Disclosed is a method of manufacturing semiconductor devices. A dummy gate structure is formed on a pattern area defined by an edge area of a substrate. An...
2016/0293727 FIN FIELD-EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF
A method for fabricating a FinFET structure comprises providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate; forming a...
2016/0293726 PATTERNED STRUCTURE OF A SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF
A patterned structure of a semiconductor device includes a substrate, a first feature and a second feature. The first feature and the second feature are...
2016/0293725 SEMICONDUCTOR DEVICE HAVING METAL GATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING METAL GATE
A method for manufacturing a semiconductor device having metal gate includes following steps. A substrate is provided. At least a transistor including a dummy...
2016/0293724 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
A method for fabricating a semiconductor device includes: forming a silicon nitride film having a refractive index equal to or larger than 2.2 on a nitride...
2016/0293723 High Electron Mobility Transistor and Method of Forming the Same
A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different...
2016/0293722 ELECTRICAL CONTACT
The present invention relates to an electrical contact. In particular, it relates to an electrical contact capable of establishing an electrical contact with a...
2016/0293721 CONTACT FOR HIGH-K METAL GATE DEVICE
An integrated circuit having an improved gate contact and a method of making the circuit are provided. In an exemplary embodiment, the method includes...
2016/0293720 Memory First Process Flow and Device
A semiconductor device includes a substrate comprising a source region and a drain region, a bit storing element formed on the substrate, a memory gate...
2016/0293719 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes a control gate electrode and a memory gate electrode which are formed over the main surface of a semiconductor substrate in a...
2016/0293718 FINFET CONFORMAL JUNCTION AND ABRUPT JUNCTION WITH REDUCED DAMAGE METHOD AND DEVICE
A method of forming a source/drain region with abrupt vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a...
2016/0293717 SEMICONDUCTOR DEVICE HAVING CONTACT PLUGS
A semiconductor device includes a substrate having an upper surface, a plurality of active fins on the substrate, a gate electrode crossing the plurality of...
2016/0293716 THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, ARRAY SUBSTRATE, AND DISPLAY DEVICE
The present disclosure provides a thin film transistor and its manufacturing method, an array substrate, a display device. The thin film transistor includes a...
2016/0293715 SEMICONDUCTOR STRUCTURE HAVING SOURCE/DRAIN GOUGING IMMUNITY
There is set forth herein a method of fabricating a semiconductor structure, the method including forming a conductive metal layer over a source/drain region....
2016/0293714 SEMICONDUCTOR DEVICE COMPRISING PLANAR GATE AND TRENCH FIELD ELECTRODE STRUCTURE
An embodiment of a semiconductor device includes a transistor cell array having transistor cells in a semiconductor body. A planar gate structure is on the...
2016/0293713 MULTICHANNEL DEVICES WITH GATE STRUCTURES TO INCREASE BREAKDOWN VOLTAGE
A transistor device is provided that includes a base structure and a superlattice structure that overlies the base structure. The superlattice structure...
2016/0293712 SEMICONDUCTOR WAFER AND MANUFACTURING METHOD
A semiconductor wafer includes first and second main surfaces opposite to each other along a vertical direction, and a side surface encircling the ...
2016/0293711 Substrate For Molecular Beam Epitaxy (MBE) HGCDTE Growth
A semiconductor structure having a first semiconductor body having an upper surface with a non <211> crystallographic orientation and a second...
2016/0293710 NITRIDE SEMICONDUCTOR SUBSTRATE
A solution is formation of a nitride semiconductor layer on one principal plane of a single crystal substrate through a first layer. Upon selecting arbitrary...
2016/0293709 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
Characteristics of a semiconductor device are improved. A semiconductor device includes a voltage clamp layer, a channel base layer, a channel layer, and a...
2016/0293708 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating film, and a gate electrode. The gate insulating film is provided...
2016/0293707 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate, an initial layer, and a buffer stack structure. The initial layer is located on the substrate and includes...
2016/0293706 FINFET SEMICONDUCTOR DEVICES WITH STRESSED CHANNEL REGIONS
A FinFET device includes a substrate, a gate structure positioned above the substrate, and sidewall spacers positioned adjacent to the gate structure. An epi...
2016/0293705 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a multi-channel active pattern including germanium...
2016/0293704 HYBRID ASPECT RATIO TRAPPING
A semiconductor structure includes a material stack located on a surface of a semiconductor substrate. The material stack includes, from bottom to top, a...
2016/0293703 Field Effect Transistors and Methods of Forming Same
Semiconductor devices and methods of forming the same are provided. A semiconductor device includes a substrate, the substrate having a first source/drain...
2016/0293702 STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a ...
2016/0293701 SEMICONDUCTOR STRUCTURE HAVING ENLARGED REGROWTH REGIONS AND MANUFACTURING METHOD OF THE SAME
The present disclosure provides a semiconductor structure, including: an insulation region including a top surface; a semiconductor fin protruding from the top...
2016/0293700 HETEROJUNCTION BIPOLAR TRANSISTOR ARCHITECTURE
A transistor includes a sub-collector, a base, a collector between the sub-collector and the base, and an emitter on the base opposite the collector. The...
2016/0293699 FORMING MULTI-STACK NANOWIRES USING A COMMON RELEASE MATERIAL
A method for forming a multi-stack nanowire device includes forming a common release layer on a substrate, the common release layer comprising a common release...
2016/0293698 POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
A power semiconductor device is provided. The power semiconductor device includes a substrate having a device region and a surrounding termination region; and...
2016/0293697 SEMICONDUCTOR DEVICES INCLUDING ACTIVE FINS AND METHODS OF MANUFACTURING THE SAME
Semiconductor devices may include a plurality of active fins each extending in a first direction on a substrate, a gate structure extending on the active fins...
2016/0293696 HIGH VOLTAGE RESISTOR WITH PIN DIODE ISOLATION
Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located...
2016/0293695 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
The present disclosure provides a semiconductor device, comprising: a substrate having a first semiconductor material; a second semiconductor layer on the...
2016/0293694 HIGH VOLTAGE RESISTOR WITH HIGH VOLTAGE JUNCTION TERMINATION
High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a first doped region and a second doped region disposed in...
2016/0293693 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A first parallel pn layer in which first n-type regions and first p-type regions are disposed in a plan view layout of stripes in an element active portion. A...
2016/0293692 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A first parallel pn layer having a first n-type region and a first p-type region junctioned alternately and repeatedly is disposed in an element active...
2016/0293691 Semiconductor Device With Channelstopper and Method for Producing the Same
A vertical semiconductor device comprises a substrate having a front surface and a back surface, an active area (AA) located in the substrate, having a drift...
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