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Patent # Description
2016/0293590 Mask Optimization For Multi-Layer Contacts
A semiconductor device includes two elongated active regions that include source/drain regions for multiple transistor devices, a first contact layer that...
2016/0293589 TECHNIQUE FOR FABRICATION OF MICROELECTRONIC CAPACITORS AND RESISTORS
A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate...
2016/0293588 Process for Forming Package-on-Package Structures
A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the...
2016/0293587 Optoelectronic Semiconductor Apparatus and Carrier Assembly
A semiconductor apparatus with an optoelectronic device and a further device is disclosed. Embodiments of the invention provide a semiconductor apparatus with...
2016/0293586 METHOD OF INTEGRATING INORGANIC LIGHT EMITTING DIODE WITH OXIDE THIN FILM TRANSISTOR FOR DISPLAY APPLICATIONS
A method of fabricating an active matrix display is disclosed in which one or more oxide thin film transistors is monolithically integrated with an inorganic...
2016/0293585 COMPACT OPTOELECTRONIC MODULES
Compact optoelectronic modules are described that, in some implementations, can have reduced heights, while at the same time having very little optical...
2016/0293584 Three-Dimensional Vertical Memory Comprising Dice with Different Interconnect Levels
The present invention discloses a three-dimensional vertical memory (3D-M.sub.V). It comprises at least a 3D-array die and at least a peripheral-circuit die....
2016/0293583 SEMICONDUCTOR INTEGRATED CIRCUIT
A semiconductor integrated circuit according to an embodiment includes: a CMOS inverter including an n-channel transistor and a p-channel transistor, one of...
2016/0293582 SEMICONDUCTOR DEVICE
A semiconductor device includes a first semiconductor chip having a first surface, a second surface on a side of the first semiconductor chip opposite to that...
2016/0293581 SEMICONDUCTOR PACKAGE ASSEMBLY WITH EMBEDDED IPD
The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first...
2016/0293580 SYSTEM IN PACKAGE AND METHOD FOR MANUFACTURING THE SAME
Disclosed herein is a system in package and a method of manufacturing the same. The system in package includes a first semiconductor die including a plurality...
2016/0293579 INTEGRATION STRUCTURES FOR HIGH CURRENT APPLICATIONS
Through-silicon-vias (TSV) to back end of line (BEOL) integration structures and a method of manufacturing the same are disclosed. Embodiments include...
2016/0293578 MULTI-CHIP-MODULE SEMICONDUCTOR CHIP PACKAGE HAVING DENSE PACKAGE WIRING
An apparatus is described having a build-up layer. The build-up layer has a pad side of multiple die pressed into a bottom side of the build-up layer. The...
2016/0293577 Chip on Package Structure and Method
A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over...
2016/0293576 Packaging Methods for Semiconductor Devices, Packaged Semiconductor Devices, and Design Methods Thereof
Packaging methods for semiconductor devices, packaged semiconductor devices, and design methods thereof are disclosed. In some embodiments, a method of...
2016/0293575 SYSTEM-IN-PACKAGE AND FABRICATION METHOD THEREOF
A system-in-package (SiP) includes a RDL structure having a first side and a second side opposite to the first side; a first semiconductor die mounted on the...
2016/0293574 STACKED PACKAGE CONFIGURATIONS AND METHODS OF MAKING THE SAME
Some examples of the disclosure may include a package on package integrated package configuration including a first die located above the substrate in a first...
2016/0293573 FLEXIBLE-SUBSTRATE-BASED THREE-DIMENSIONAL PACKAGING STRUCTURE AND METHOD
The present invention mainly relates to a 3-D packaging structure based on a flexible substrate and a method for manufacturing the same; the method comprises:...
2016/0293572 CAVITY BRIDGE CONNECTION FOR DIE SPLIT ARCHITECTURE
An integrated circuit (IC) package structure may include a substrate. The substrate may include a semiconductor bridge having a first surface directly on a...
2016/0293571 STRETCHABLE DISPLAY
A stretchable display is disclosed. In one aspect, the stretchable display includes a plurality of pixel substrates arranged in a matrix having row and column...
2016/0293570 ELECTRONIC CONNECTION STRUCTURE FOR COUPLING PINS OF CHIP WITH WIRING CIRCUIT AND PANEL USING SAME
An electronic connection structure includes a first connection portion, a second connection portion, and a connection pad configured to be coupled the first...
2016/0293569 SEMICONDUCTOR DEVICE MANUFACTURING METHOD
In wire bonding in assembling of a semiconductor device, an Al wire is coupled to a lead section by a wedge which is a bonding tool, thereafter, the wedge is...
2016/0293568 METHODS FOR FORMING SEMICONDUCTOR DEVICE PACKAGES
A semiconductor device package that incorporates a combination of ceramic, organic, and metallic materials that are coupled using silver is provided. The...
2016/0293567 HYBRID BONDING SYSTEM AND CLEANING METHOD THEREOF
In some embodiments, a hybrid bonding system includes a first device, a second device and a first cleaning module. The first device is configured to load a...
2016/0293566 MICRO DEVICE TRANSFER SYSTEM WITH PIVOT MOUNT
Systems and methods for transferring a micro device from a carrier substrate are disclosed. In an embodiment, a micro pick up array mount includes a pivot...
2016/0293565 SEMICONDUCTOR PACKAGES WITH SOCKET PLUG INTERCONNECTION STRUCTURES
A semiconductor package may include a first substrate and a second substrate. Socket bumps may be disposed on the first substrate to provide insertion grooves...
2016/0293564 SEMICONDUCTOR DEVICE
Reliability of a semiconductor device is improved. A semiconductor device has a base material of insulating material having a through hole, a terminal formed...
2016/0293563 ELECTRODE TERMINAL, SEMICONDUCTOR DEVICE FOR ELECTRICAL POWER, AND METHOD FOR MANUFACTURING SEMICONDUCTOR...
An electrode terminal includes: a first drawn-out part to be bonded to a main electrode; and a second drawn-out part that is formed of a plate member in a...
2016/0293562 POWER MODULE SUBSTRATE, METHOD OF PRODUCING SAME, AND POWER MODULE
An elongated trench (35) is formed so as to connect the Ag layer (32) and the exposed part of the circuit layer stretching out around the Ag layer (32). The...
2016/0293561 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate, a semiconductor element, a terminal and a solder outflow prevention part. The semiconductor element is fixed on...
2016/0293560 SEMICONDUCTOR DEVICE INCLUDING SUPPORT PILLARS ON SOLDER MASK
A semiconductor device, and a method of its manufacture, are disclosed. The semiconductor device includes a substrate having a solder mask. A plurality of...
2016/0293559 SEMICONDUCTOR PACKAGES WITH PILLAR AND BUMP STRUCTURES
One or more embodiments are directed to semiconductor packages that include a pillar and bump structures. The semiconductor packages include a die that has...
2016/0293558 Semiconductor Device and Method of Forming Wafer Level Ground Plane and Power Ring
A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the...
2016/0293557 PACKAGE AND ANTENNA APPARATUS INCLUDING PACKAGE
A package for embedding one or more electronic components comprises a carrier structure a silicon-based carrier layer, one or more electronic components...
2016/0293556 WARPAGE REDUCTION IN STRUCTURES WITH ELECTRICAL CIRCUITRY
To reduce warpage in at least one area of a wafer, a stress/warpage management layer (810) is formed to over-balance and change the direction of the existing...
2016/0293555 MOLD PACKAGE
A mold package being a half-mold type includes: a substrate includes a first face and a second face; an electronic component that is mounted on the first face;...
2016/0293554 A GUARD STRUCTURE FOR SIGNAL ISOLATION
A method of fabricating an electrical guard structure for providing signal isolation is provided. The method includes providing a substrate having a mounting...
2016/0293553 EMI SHIELDING METHOD OF SEMICONDUCTOR PACKAGES
Disclosed is an EMI shielding method of semiconductor packages, including a tape attaching step of attaching an edge of a tape to a lower side of a frame to...
2016/0293552 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
A semiconductor device includes an insulating interlayer on a first region of a substrate. The insulating interlayer has a recess therein and includes a low-k...
2016/0293551 INTEGRATED ELECTRONIC PACKAGE AND STACKED ASSEMBLY THEREOF
A wafer level packaging method entails providing electronic devices and providing a platform structure having cavities extending through the platform...
2016/0293550 SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME
In one embodiment, a method of fabricating a semiconductor package includes forming a first plurality of die openings on a laminate substrate. The laminate...
2016/0293549 Compound Semiconductor Device Including a Sensing Lead
A device includes a compound semiconductor chip having a control electrode, a first load electrode and a second load electrode. A first lead is electrically...
2016/0293548 METHOD AND CIRCUITS FOR COMMUNICATION IN MULTI-DIE PACKAGES
Various example implementations are directed to circuits and methods for inter-die communication on a multi-die integrated circuit (IC) package. According to...
2016/0293547 SEMICONDUCTOR DEVICES INCLUDING A CAPPING LAYER
Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and...
2016/0293546 Semiconductor Devices and Methods for Manufacturing the Same
The inventive concepts relate to a semiconductor device including a field effect transistor and a method for manufacturing the same. The semiconductor device...
2016/0293545 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a substrate including PMOSFET and NMOSFET regions, a first gate structure extending in a first direction and crossing the...
2016/0293544 INDUCTOR ASSEMBLY AND METHOD OF USING SAME
An inductor assembly generally comprises at least one helical inductive component comprising that includes a plurality of conductive line layers having...
2016/0293543 Compound Semiconductor Device Including a Multilevel Carrier
A device includes a carrier having a first carrier section on a first level and a second carrier section on a second level different from the first level. The...
2016/0293542 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME
For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is...
2016/0293541 STRUCTURED INTEGRATED CIRCUIT DEVICE WITH MULTIPLE CONFIGURABLE VIA LAYERS
An integrated circuit may include a multi-layer structure having alternating metal interconnection layers and via layers superimposed on a base layer having...
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