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Patent # Description
2016/0293290 COMPOSITIONS FOR PREPARING ELECTRICALLY CONDUCTIVE COMPOSITES, COMPOSITES PREPARED THEREFROM, AND ELECTRONIC...
A composition for preparing an electrically conductive composite includes, based on the total weight of the composition: about 37 weight percent to about 84...
2016/0293289 METHOD FOR STRUCTURING A TRANSPARENT CONDUCTIVE MATRIX COMPRISING NANO MATERIALS
The present invention refers to a method for selectively structuring of a polymer matrix comprising AgNWs (silver nano wires) or silver nano particles (Ag nano...
2016/0293288 TRANSPARENT CONDUCTIVE FILM
Metal nanowires with uniform noble metal coatings are described. Two methods, galvanic exchange and direct deposition, are disclosed for the successful...
2016/0293287 Method Of Providing Electrical Conductivity Properties In Biocomposite Materials
A method to provide enhanced electrical conductivity to the biocomposite material in which fibrous materials are initially combined and mixed with a polymer...
2016/0293286 CONDUCTIVE COMPLEX AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE INCLUDING THE CONDUCTIVE COMPLEX
A conductive complex includes a conductive nanobody network including a plurality of conductive nanobodies randomly arranged, and an overcoat layer including...
2016/0293285 SCINTILLATOR PANEL
The present invention is a scintillator panel including: a substrate, a barrier rib formed on the substrate, and a scintillator layer containing a phosphor...
2016/0293284 Metal Grating Structure For X-Ray
A metal grating structure for X-ray includes a first silicon part having a plate form or a layer form, and a grating portion, wherein the grating portion...
2016/0293283 ISOTOPE-SPECIFIC SEPARTION AND VITRIFICTION
Apparatuses, processes and methods for the separation, isolation, or removal of radioactive isotopes from liquid radioactive waste, these processes and methods...
2016/0293282 System for Deep Underground Storage of Radioactive Waste
A system for the storage of a radioactive waste product, wherein the radioactive waste product is located in a container and where one or more containers are...
2016/0293281 Nuclear Power Plant
When a power source is lost after an operation stop of a nuclear power plant, a first open/close valve is opened via a first battery at an early stage and...
2016/0293280 CRDM INTERNAL HYDRAULIC CONNECTOR
In a nuclear reactor, an internal control rod drive mechanism (CRDM) includes a motor and a hydraulically driven element connected by at least one hydraulic...
2016/0293279 DIELECTRIC WALL ACCELERATOR AND APPLICATIONS AND METHODS OF USE
Provided are a plurality of embodiments, including, but not limited to, a device for generating efficient low and high average power output Gamma Rays via...
2016/0293278 SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF
A semiconductor memory device may include: a plurality of first to third memory cells, each memory cell being a DRAM memory cell; a plurality of fuses suitable...
2016/0293277 MEMORY DEVICE WITH REDUNDANT IO CIRCUIT
A device includes input/output (IO) circuits, a redundant IO circuit and a redundant IO control unit. The input/output (IO) circuits coupled to a memory array....
2016/0293276 TEST METHOD OF SEMICONDUCTOR DEVICE
The semiconductor device includes a bit line, a transistor, a retention node, and a capacitor. The transistor has a function of charging or discharging the...
2016/0293275 SEMICONDUCTOR MEMORY DEVICE OUTPUTTING STATUS FAIL SIGNAL AND OPERATING METHOD THEREOF
In a method of operating a semiconductor memory device, a program command is received, and a program operation is performed to increase threshold voltages of...
2016/0293274 Storage Device Firmware and Manufacturing Software
Storage device FirmWare (FW) and manufacturing software techniques include access to FW images and communication of a manufacturing software tool. The...
2016/0293273 CACHE MEMORY DIAGNOSTIC WRITEBACK
A processor includes a cache memory having a plurality of entries. Each of the entries holds data of a cache line, a state of the cache line and a tag of the...
2016/0293272 METHOD AND APPARATUS FOR OPTIMIZED MEMORY TEST STATUS DETECTION AND DEBUG
Embodiments contained in the disclosure provide a method for memory built-in self-testing (MBIST). The method begins when a testing program is loaded, which...
2016/0293271 SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF
A method of operating a semiconductor memory device includes applying a program pulse at least once to each of a plurality of pages; performing a pre-read...
2016/0293270 ARRAY SUBSTRATE AND METHOD FOR FORMING THE SAME
An array substrate and a method for forming the same are provided. The array substrate includes: a gate driver in a non-display area, wherein the gate driver...
2016/0293269 SHIFT REGISTER AND DISPLAY DEVICE HAVING THE SAME
There is provided a shift register including a plurality of stages sequentially coupled to an input terminal configured to receive a start pulse, wherein each...
2016/0293268 Implementation of a One Time Programmable Memory Using a MRAM Stack Design
An integrated circuit includes a magnetic OTP memory array formed of multiple magnetic OTP memory cells having an MTJ stack with a fixed magnetic layer, a...
2016/0293267 SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
A semiconductor memory device includes a command buffering unit suitable for receiving and buffering a command signal based on an enable control signal, a fuse...
2016/0293266 Temperature Dependent Voltage To Unselected Drain Side Select Transistor During Program Of 3D NAND
Techniques are provided for reducing program disturb in a 3D memory device. The techniques include compensating for a temperature dependence of program...
2016/0293265 CLOCK MODE DETERMINATION IN A MEMORY SYSTEM
A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other,...
2016/0293264 AD HOC DIGITAL MULTI-DIE POLLING FOR PEAK ICC MANAGEMENT
Systems and methods for reducing peak power supply current in a non-volatile memory system that includes a plurality of memory die are described. In some...
2016/0293263 NONVOLATLE MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME, AND RELATED MEMORY MANAGEMENT, ERASE AND...
An erase method of a nonvolatile memory device includes setting an erase mode, and performing one of a normal erase operation and a quick erase operation...
2016/0293262 FLASH MEMORY COUNTER
A method of updating a counter in a flash memory includes a first phase where a set of values capable of being taken by the counter are programmed in at least...
2016/0293261 MEMORY UNIT WITH VOLTAGE PASSING DEVICE
A memory cell includes a floating gate transistor, a word line transistor, a first capacitance element, and a second capacitance element. The floating gate...
2016/0293260 Method And Apparatus For Inhibiting The Programming Of Unselected Bitlines In A Flash Memory System
Various embodiments for inhibiting the programming of memory cells coupled to unselected bit lines while programming a memory cell coupled to a selected bit...
2016/0293259 SEMICONDUCTOR APPARATUS AND OPERATING METHOD THEREOF
A nonvolatile memory apparatus includes a plurality of memory cells coupled to a word line and respectively coupled to different bit lines, and a control block...
2016/0293258 NONVOLATILE MEMORY DEVICE, PROGRAM METHOD THEREOF, AND STORAGE DEVICE INCLUDING THE SAME
A nonvolatile memory device includes memory cells stacked in a direction perpendicular to a substrate and further includes a first memory cell string connected...
2016/0293257 SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELLS EACH INCLUDING A CHARGE ACCUMULATION LAYER AND A CONTROL GATE
A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control...
2016/0293256 Two Transistor SONOS Flash Memory
A two transistor SONOS flash memory is disclosed. In one aspect, an apparatus, includes a control gate transistor having source and drain diffusions deposited...
2016/0293255 MULTIPLEXER-BASED TERNARY CONTENT ADDRESSABLE MEMORY
In one example, a ternary content addressable memory (TCAM) includes an input port coupled to receive a W-bit key as input, and an output port coupled to...
2016/0293254 APPARATUSES AND METHODS INCLUDING MEMORY ACCESS IN CROSS POINT MEMORY
Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch...
2016/0293253 SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor memory device includes a memory cell including a variable resistance element, a first circuit including a first...
2016/0293252 SEMICONDUCTOR STORAGE DEVICE
According to one embodiment, a semiconductor storage device includes: a first memory cell; a first bit line coupled to the first memory cell; and a first...
2016/0293251 SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor memory device includes: a plurality of memory cells, each of which including a memory element and a first switch...
2016/0293250 Charge Loss Compensation Through Augmentation of Accumulated Charge in a Memory Cell
Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a block of solid-state non-volatile...
2016/0293249 SEMICONDUCTOR STORAGE DEVICE
A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is...
2016/0293248 STATIC RANDOM ACCESS MEMORY AND METHOD OF OPERATING THE SAME
A static random access memory (SRAM) including at least a memory cell array, a first data line, a second data line, a third data line and a driver circuit. The...
2016/0293247 Read-Write Contention Circuitry
Various implementations described herein are directed to an integrated circuit for read-write contention. The integrated circuit may include a memory circuit...
2016/0293246 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device according to an embodiment includes first and second storages that enable writing and reading of data. The first decoding line...
2016/0293245 CIRCUIT STRUCTURE FOR SUPPRESSING ELECTROMAGNETIC INTERFERENCE OF DDR SDRAM SIGNALS
A circuit structure for suppressing electromagnetic interference (EMI) of DDR SDRAM signals, applied to a memory interface unit (MIU) of a DDR SDRAM, includes:...
2016/0293244 VOLATILE MEMORY ERASURE BY MANIPULATING REFERENCE VOLTAGE OF THE MEMORY
The present invention provides an erasure circuitry, a method for erasing a volatile memory, a volatile memory and erasure module in the form of computer...
2016/0293243 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device may include a memory bank having a plurality of word lines arranged at a predetermined address interval, an address latching unit...
2016/0293242 SYSTEMS, METHODS, AND APPARATUSES FOR PERFORMING REFRESH OPERATIONS
Methods, apparatuses, and systems for performing refresh operations on a memory cell array that does not have an Nth-power-of-2 number of memory mats are...
2016/0293241 NONVOLATILE MEMORY INTERFACE FOR METADATA SHADOWING
A memory includes non-volatile memory devices, each of which has multiple nonvolatile memory cells. A write controller streams bits to the memory devices in...
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