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Patent # Description
2016/0300798 DIRECTIONAL COUPLER
Directional couplers are used to detect forward power delivered by a power amplifier. Mechanisms are provided herein which improve the accuracy of the power...
2016/0300797 Double-Sided Semiconductor Package and Dual-Mold Method of Making Same
A semiconductor device comprises a first conductive layer formed on a carrier over an insulating layer. A portion of the insulating layer is removed prior to...
2016/0300796 RELIABLE MICROSTRIP ROUTING FOR ELECTRONICS COMPONENTS
Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having...
2016/0300795 SEMICONDUCTOR DEVICES INCLUDING EMPTY SPACES AND METHODS OF FORMING THE SAME
Semiconductor devices including empty spaces and methods of forming the semiconductor devices are provided. The semiconductor devices may include first and...
2016/0300794 Stress Reduction Apparatus
A device comprises a metal via having a lower portion in a first etch stop layer and an upper portion in a first dielectric layer over a substrate, a second...
2016/0300793 WAFER WITH PLATED WIRES AND METHOD OF FABRICATING SAME
An aspect of the invention includes a method for plating wires on a wafer comprising: forming an array of integrated circuit (IC) chips having a redistribution...
2016/0300792 SEMICONDUCTOR DEVICES
Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer....
2016/0300791 SEMICONDUCTOR DEVICES
There is provided a semiconductor device having an arrangement structure in which high-density line patterns having relatively small widths and relatively...
2016/0300790 PACKAGE SUBSTRATES AND METHODS OF FABRICATING THE SAME
A package substrate includes a core portion comprising a first surface and a second surface arranged opposite to each other; first cutting regions provided to...
2016/0300789 Packaged Semiconductor Devices and Methods of Packaging Semiconductor Devices
Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an...
2016/0300788 INTERPOSER AND METHODS OF FORMING AND TESTING AN INTERPOSER
A method of forming and testing an interposer includes forming vias in a semiconductor material of a wafer having a front side and a back side. The method...
2016/0300787 SUBSTRATES AND SEMICONDUCTOR PACKAGES INCLUDING THE SAME, ELECTRONIC SYSTEMS INCLUDING THE SEMICONDUCTOR...
A substrate may include a body having a first surface and a second surface opposite to each other, at least one first wiring pattern disposed on the first...
2016/0300786 PLATED TERMINALS WITH ROUTING INTERCONNECTIONS SEMICONDUCTOR DEVICE
A semiconductor package includes terminals, each having an exposed surface that is flush with a bottom surface of the semiconductor package, and a layer of...
2016/0300785 POWER SEMICONDUCTOR DEVICE
Projections 35 provided in a base plate 22 are fitted into notches provided in an electrically conductive member 12, and then the base plate 22 is fixed to the...
2016/0300784 FLIPPABLE LEADFRAME FOR PACKAGED ELECTRONIC SYSTEM HAVING VERTICALLY STACKED CHIPS AND COMPONENTS
A leadframe (100) for electronic systems comprising a first sub-leadframe (110) connected by links (150) to a second sub-leadframe (120), the first and second...
2016/0300783 PLATED TERMINALS WITH ROUTING INTERCONNECTIONS SEMICONDUCTOR DEVICE
A semiconductor package includes terminals, each having an exposed surface that is flush with a bottom surface of the semiconductor package, and a layer of...
2016/0300782 SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
The present disclosure relates to a semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes a...
2016/0300781 CAVITY PACKAGE WITH COMPOSITE SUBSTRATE
An integrated device package is disclosed. The package can include a package substrate comprising a composite die pad having an upper surface and a lower...
2016/0300780 LIQUID COOLED COMPLIANT HEAT SINK AND RELATED METHOD
A heat sink and method for using the same for use in cooling an integrated circuit (IC) chip is provided herein. The heat sink includes a manifold block, a...
2016/0300779 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
Thermal resistance is reduced from an element surface of a semiconductor chip to the rear surface of a semiconductor package. Split patterning of a metal is...
2016/0300778 SEMICONDUCTOR DEVICE
A semiconductor device includes an insulating substrate having a metal plate, an insulating resin plate, and a circuit plate laminated in order; a...
2016/0300777 POWER MODULE AND THERMAL INTERFACE STRUCTURE THEREOF
A power module and a thermal interface structure are provided herein. The thermal interface structure includes: a base and a plurality of filler particles...
2016/0300776 SEMICONDUCTOR DEVICE
A semiconductor device includes two or more semiconductor elements, a lead with island portions on which the semiconductor elements are mounted, a heat...
2016/0300775 INTEGRATION OF HEAT SPREADER FOR BEOL THERMAL MANAGEMENT
A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader...
2016/0300774 SEMICONDUCTOR PACKAGE INCLUDING HEAT SPREADER AND METHOD FOR MANUFACTURING THE SAME
A semiconductor package includes a semiconductor chip on a package substrate, a heat spreader on the semiconductor chip, a molding layer, an adhesive film...
2016/0300773 PRINTED CIRCUIT BOARD, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
There is provided a printed circuit board includes a substrate having product areas for mounting elements and dummy areas disposed between two neighboring...
2016/0300772 LIQUID SEALING MATERIAL AND ELECTRONIC COMPONENT USING SAME
A liquid sealing material which has excellent PCT (pressure cooker test) resistance, and an electronic component which is obtained by sealing a part to be...
2016/0300771 CHIP PACKAGE AND METHOD FOR FABRICATING THE SAME
A method for fabricating chip package includes providing a semiconductor chip with a metal bump, next adhering the semiconductor chip to a substrate using a...
2016/0300770 POWER MODULE AND METHOD OF MANUFACTURING POWER MODULE
A power module providing an improved manufacture yield and having an ensured stable joint strength and accordingly improved reliability is provided. The power...
2016/0300769 ENCAPSULATION SYSTEM AND ENCAPSULATION METHOD
The present disclosure discloses an encapsulation system and an encapsulation method, the encapsulation system comprising a thickness detection unit, an output...
2016/0300768 METHOD FOR EVALUATING CONCENTRATION OF DEFECT IN SILICON SINGLE CRYSTAL SUBSTRATE
A method for evaluating concentration of defect in silicon single crystal substrate, defect being formed by particle beam irradiation in silicon single crystal...
2016/0300767 METHOD FOR DETECTING OVERLAY ERROR AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME
A method for detecting an overlay error includes: forming a first overlay key including a plurality of spaced apart first target patterns having a first pitch...
2016/0300766 METHOD FOR DESIGNING LAYOUT OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE...
A method of manufacturing a semiconductor device includes providing pre-conductive lines and post-conductive lines for forming a first logic cell and a second...
2016/0300765 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A method for manufacturing a semiconductor device is provided. A substrate with an insulation formed thereon is provided, wherein the insulation has plural...
2016/0300764 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A piece of first connecting wiring 210 is formed of a lower layer wiring close to a semiconductor element. A piece of second connecting wiring 220 is formed of...
2016/0300763 SEMICONDUCTOR DEVICES INCLUDING A BIT LINE STRUCTURE AND A CONTACT PLUG
Semiconductor devices are provided. A semiconductor device includes a bit line structure and a contact plug. The contact plug is adjacent a sidewall of the bit...
2016/0300762 SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED GATE CONTACTS
A semiconductor device and a method for manufacturing the device. The method includes: depositing a first dielectric layer on a semiconductor device; forming a...
2016/0300761 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A method of fabricating a semiconductor device is provided. A dielectric layer is formed on a barrier layer. A first opening is formed in the dielectric layer...
2016/0300760 Protecting Layer in a Semiconductor Structure
A method for forming a protecting layer includes determining an expected concentration of metal ions in a dielectric layer. The method also includes...
2016/0300759 Method for Coating a Substrate
A method for coating substrates provided with vias uses a first step in which the substrate is conditioned and a second step in which the substrate is coated...
2016/0300758 METHOD FOR FORMING COBALT BARRIER LAYER AND METAL INTERCONNECTION PROCESS
The present invention provides a method for forming a cobalt barrier layer and a metal interconnection process. The method is performed on a surface of a...
2016/0300757 DIELECTRIC CONSTANT RECOVERY
A method of forming features in a low-k dielectric layer on a patterned substrate is described. A via, trench or a dual damascene structure may be formed in...
2016/0300756 SUBTRACTIVE METHODS FOR CREATING DIELECTRIC ISOLATION STRUCTURES WITHIN OPEN FEATURES
A method for partially filling an open feature on a substrate includes receiving a substrate having a layer with at least one open feature formed therein,...
2016/0300755 SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF
A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap...
2016/0300754 METHODS FOR FABRICATING INTEGRATED CIRCUITS USING MULTI-PATTERNING PROCESSES
Methods for fabricating integrated circuits are provided. One method includes decomposing a master pattern layout for a semiconductor device layer that...
2016/0300753 SUSCEPTOR, VAPOR DEPOSITION APPARATUS, VAPOR DEPOSITION METHOD AND EPITAXIAL SILICON WAFER
A disc-shaped susceptor includes a plurality of recesses that are aligned in a circumferential direction on an upper surface of the susceptor and in which...
2016/0300752 SUPPORT CYLINDER FOR THERMAL PROCESSING CHAMBER
Embodiments of the disclosure generally relate to a support cylinder used in a thermal process chamber. In one embodiment, the support cylinder includes a...
2016/0300751 Wafer Treating Device and Sealing Ring for a Wafer Treating Device
A sealing ring for attaching to a cover ring of a wafer treating device has an annular carrier and a sealing lip which is releasably attached to the carrier.
2016/0300750 HOLDING EQUIPMENT
Holding equipment for holding a plate-like member by discharging fluid to generate a negative pressure between the holding equipment and the member, includes a...
2016/0300749 HOLDING EQUIPMENT, HOLDING SYSTEM, CONTROL METHOD, AND CONVEYANCE EQUIPMENT
Swirl flow-forming body for holding a plate-like member by discharging fluid to generate a negative pressure between the swirl flow-forming body and the member...
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