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Patent # Description
2016/0308037 SEMICONDUCTOR DEVICE
A semiconductor device including a substrate, an active portion and a well region both formed in the substrate on a first surface side thereof, and a...
2016/0308036 Insulated Gate Bipolar Transistor Structure Having Low Substrate Leakage
A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), and more particularly an insulated gate bipolar junction transistor (IGBT), is...
2016/0308035 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another...
2016/0308034 METHOD FOR REPAIRING OXIDE THIN FILM AND OXIDE THIN-FILM DEVICE
Disclosed is a method for repairing an oxide thin film, including repairing the oxide thin film by forming a repairing material that contains an oxide at a...
2016/0308033 OXIDE-NITRIDE-OXIDE STACK HAVING MULTIPLE OXYNITRIDE LAYERS
An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the...
2016/0308032 PRE-SCULPTING OF SI FIN ELEMENTS PRIOR TO CLADDING FOR TRANSISTOR CHANNEL APPLICATIONS
Transistor fin elements (e.g., fin or tri gate) may be modified by radio frequency (RF) plasma and/or thermal processing for purpose of dimensional sculpting....
2016/0308031 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device comprises a substrate, a gate structure and a gate spacer. The substrate has a semiconductor fin protruding from a surface of the...
2016/0308030 SEMICONDUCTOR DEVICE HAVING A GATE THAT IS BURIED IN AN ACTIVE REGION AND A DEVICE ISOLATION FILM
A semiconductor device includes an active region with a first gate trench formed when a gate region is etched to a first depth, a device isolation film...
2016/0308029 PREPARATION METHOD FOR POWER DIODE
A preparation method for a power diode, comprising: providing a substrate (10), the substrate (10) having a front surface and a back surface opposite to the...
2016/0308028 Method of Forming a Trench Using Epitaxial Lateral Overgrowth
In one aspect, a method of forming a trench in a semiconductor material includes forming a first dielectric layer on a semiconductor substrate. The first...
2016/0308027 PROCESS OF MANUFACTURING FIN-FET DEVICE
A process of manufacturing a Fin-FET device, and the process includes following steps. An active fin structure and a dummy fin structure are formed from a...
2016/0308026 REPLACEMENT METAL GATE DIELECTRIC CAP
A method for manufacturing a field effect transistor includes chelating a molecular mask to a replacement metal gate in a field effect transistor. The method...
2016/0308025 REPLACEMENT CHANNEL TFET
A semiconductor structure includes a substrate and an intrinsic replacement channel. A tunneling field effect transistor (TFET) fin may be formed by the...
2016/0308024 Rectifier Structures with Low Leakage
An integrated circuit device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a gate dielectric over...
2016/0308023 METHOD OF FORMING A HIGH ELECTRON MOBILITY TRANSISTOR
A method of forming a high electron mobility transistor (HEMT) that includes epitaxially growing a second III-V compound layer on a first III-V compound layer....
2016/0308022 SEMICONDUCTOR DEVICE INCLUDING AN IGBT AS A POWER TRANSISTOR AND A METHOD OF MANUFACTURING THE SAME
An improvement is achieved in the performance of a semiconductor device. Over the main surface of a semiconductor substrate for the n-type base of an IGBT, an...
2016/0308021 Tunnel MOSFET with Ferroelectric Gate Stack
A Tunnel Field-Effect Transistor (TFET) includes a source region in a semiconductor substrate, and a drain region in the semiconductor substrate. The source...
2016/0308020 FABRICATING LARGE AREA MULTI-TIER NANOSTRUCTURES
Methods for fabricating and replicating self-aligned multi-tier nanoscale structures for a variety of cross-sectional geometries. These methods can utilize a...
2016/0308019 FIELD-EFFECT TRANSISTOR
The present invention provides a field-effect transistor having an accumulation-layer-operation type field-effect transistor that includes a semiconductor...
2016/0308018 GATE STACKS
Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten...
2016/0308017 FET DEVICE WITH TUNED GATE WORK FUNCTION
A method of forming a semiconductor device is provided including forming a gate structure comprising a metal-containing layer over a semiconductor layer and...
2016/0308016 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, a source/drain region in an...
2016/0308015 MOSFET with Reduced Resistance
A semiconductor device comprises a semiconductor substrate including a doped region. A metal layer is formed on the doped region. An insulating layer covers...
2016/0308014 FABRICATION OF CHANNEL WRAPAROUND GATE STRUCTURE FOR FIELD-EFFECT TRANSISTOR
A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the...
2016/0308013 SEMICONDUCTOR DEVICE AND PRODUCTION METHOD
A semiconductor device production method includes preparing a first structure having a first planar semiconductor layer, and a first columnar semiconductor...
2016/0308012 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
In a semiconductor device including a gate line having a relatively narrow width and a relatively smaller pitch and a method of manufacturing the semiconductor...
2016/0308011 MEMORY CELL COMPRISING NON-SELF-ALIGNED HORIZONTAL AND VERTICAL CONTROL GATES
The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above...
2016/0308010 SEMICONDUCTOR DEVICES WITH A THERMALLY CONDUCTIVE LAYER
An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate...
2016/0308009 Nonvolatile Charge Trap Memory Device Having A Deuterated Layer In A Multi-Layer Charge-Trapping Region
A charge trap memory device is provided. In one embodiment, the charge trap memory device includes a semiconductor material structure having a vertical channel...
2016/0308008 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Provided is a semiconductor device with a field effect transistor. The semiconductor device includes a substrate, an active pattern on the substrate, a gate...
2016/0308007 POLY SANDWICH FOR DEEP TRENCH FILL
A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon...
2016/0308006 MONOLAYER FILMS OF SEMICONDUCTING METAL DICHALCOGENIDES, METHODS OF MAKING SAME, AND USES OF SAME
Metal-chalcogenide films disposed on a substrate comprising at least one monolayer (e.g., 1 to 10 monolayers) of a metal-chalcogenide. The films can be...
2016/0308005 FINFET CONFORMAL JUNCTION AND HIGH EPI SURFACE DOPANT CONCENTRATION METHOD AND DEVICE
A method of forming a source/drain region with an abrupt, vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a...
2016/0308004 SEMICONDUCTOR DEVICES INCLUDING CONTACT STRUCTURES THAT PARTIALLY OVERLAP SILICIDE LAYERS
Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions...
2016/0308003 SEMICONDUCTOR DEVICE
A MOSFET includes: a SiC layer including one main surface and provided with a plurality of contact regions; and a plurality of source electrodes formed in...
2016/0308002 Silicide Regions in Vertical Gate All Around (VGAA) Devices and Methods of Forming Same
An embodiment semiconductor device includes a nanowire extending upwards from a semiconductor substrate, a source/drain region in the nanowire, and a channel...
2016/0308001 METHOD OF MANUFACTURING SILICON NANOWIRE ARRAY
Provided is a method for manufacturing a silicon nanowire array comprising the steps of: positioning plastic particles separated apart from one another in a...
2016/0308000 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A semiconductor device may include a semiconductor substrate including an active region defined by a trench, a device isolation layer provided in the trench to...
2016/0307999 SEMICONDUCTOR DEVICE HAVING AIR GAP AND METHOD FOR MANUFACTURING THE SAME, MEMORY CELL HAVING THE SAME AND...
A semiconductor device including a substrate including an active region and a device isolation region that isolates the active region, and a buried bit line...
2016/0307998 COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
An AlGaN/GaN HEMT includes a compound semiconductor stack structure; an element isolation structure which demarcates an element region on the compound...
2016/0307997 SEMICONDUCTOR DEVICE WITH JUNCTION TERMINATION EXTENSION
A semiconductor device may include a substrate comprising silicon carbide; a drift layer disposed over the substrate doped with a first dopant type; an anode...
2016/0307996 Semiconductor Device, Integrated Circuit and Method for Manufacturing the Semiconductor Device
A semiconductor device comprises a transistor in a semiconductor body having a first main surface and a second main surface, the first main surface being...
2016/0307995 INSULATED GATE BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREFOR
An insulated gate bipolar transistor (100) is provided. A substrate (10) of the insulated gate bipolar transistor (100) is of an N type. A P-type region (16)...
2016/0307994 METHOD FOR PREPARING POWER DIODE
A method for preparing a power diode, including: providing a substrate (10), growing a N type layer (20) on the front surface of the substrate (10); forming a...
2016/0307993 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A defective layer is formed by ion implanting argon for a p.sup.+ anode layer from a front surface side of a base substrate. Here, the range of the argon is...
2016/0307992 DEVICES, SYSTEMS, AND METHODS FOR ION TRAPPING
Devices, methods, and systems for ion trapping are described herein. One device includes a through-silicon via (TSV) and a trench capacitor formed around the TSV.
2016/0307991 Integrated Magnetic Core Inductor and Methods of Fabrications Thereof
A method of forming a semiconductor device includes forming a lower coil segment in a first dielectric layer over a substrate, forming a second dielectric...
2016/0307990 ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME
An organic light-emitting display apparatus includes a substrate including a display area and a non-display area disposed on one side of the display area, a...
2016/0307989 DISPLAY DEVICE
A display device includes, on a substrate, light emitting elements each formed by sequentially stacking a first electrode layer, an organic layer including a...
2016/0307988 Organic Light-Emitting Diode Displays with Silicon and Semiconducting Oxide Thin-Film Transistors
An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display...
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