At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A semiconductor device includes a substrate provided with active patterns, gate electrodes extending across the active patterns, source/drain regions provided...
SEMICONDUCTOR MEMORY DEVICE BIT LINE TRANSISTOR WITH DISCRETE GATE
A semiconductor memory device is provided including a plurality of diffusion region pairs comprising first and second diffusion regions, wherein each of the...
POWER MOSFET AND MANUFACTURING METHOD THEREOF
A power MOSFET includes a substrate, a dielectric layer, solder balls, first and second patterned-metal layers. The substrate includes an active surface, a...
WIRING SUBSTRATE AND METHOD FOR MANUFACTURING WIRING SUBSTRATE
A wiring substrate includes an insulating layer, a wiring layer, a via wiring, and a solder resist layer. The wiring layer includes a pad body that constitutes...
ELECTRONIC PACKAGING STRUCTURE AND METHOD FOR FABRICATING ELECTRONIC
An electronic packaging structure is provided, including a circuit portion, an electronic element disposed on an upper side of the circuit portion and a glass...
DIE STACKS WITH ONE OR MORE BOND VIA ARRAYS OF WIRE BOND WIRES AND WITH
ONE OR MORE ARRAYS OF BUMP INTERCONNECTS
An apparatus relating generally to a die stack is disclosed. In such an apparatus, a substrate is included. A first bond via array includes first wires each of...
METHOD OF MAKING A QFN PACKAGE
A method of making a flat no lead package including attaching a first plurality of leads in spaced apart relationship in a predetermined pattern on a tape and...
COMBINED PACKAGED POWER SEMICONDUCTOR DEVICE
A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal...
LEAD FRAME AND POWER MODULE
A problem to be solved is to provide a lead frame and a power module having high material yield. A lead frame includes a plurality of first leads extending to one...
ELECTRICAL CONNECTIVITY FOR CIRCUIT APPLICATIONS
According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed...
A semiconductor device includes a resin package, a semiconductor chip sealed in the package and having first and second pads on a front surface. An island of...
PACKAGING SOLUTIONS FOR DEVICES AND SYSTEMS COMPRISING LATERAL GaN POWER
Packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a...
One example discloses a lead-frame, comprising: a die-pad having a die coupling surface; a set of terminals each having an outer terminal edge and an inner...
HIGH PERFORMANCE COMPLIANT SUBSTRATE
A substrate structure is presented that can include a porous polyimide material and electrodes formed in the porous polyimide material. In some examples, a...
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a substrate including a first side, a second side opposite to the first side, and a device layer over the second side, and a...
A semiconductor device includes a semiconductor module including a semiconductor element, a passive element, a cooling member, a first conductive member and a...
COOLER AND COOLER FIXING METHOD
A cooler for cooling a semiconductor module to be secured to a base, the cooler including: a cooler body that includes a refrigerant flow path surrounded by a...
ADJUSTABLE FASTENING BRACKET FOR RADIATOR
An adjustable fastening bracket used in a radiator includes a supporting stand which includes a plate body provided with pluralities of combination grooves,...
SOLID-STATE DRIVE WITH PASSIVE HEAT TRANSFER
The disclosed embodiments relate to a system that facilitates thermal conductance in a system that includes a module comprising a circuit board with integrated...
SEMICONDUCTOR DEVICE HAVING A HEAT CONDUCTION MEMBER
A semiconductor device includes a substrate having a first surface and a second surface opposite to the first surface, a hole formed through the first and...
POWER SEMICONDUCTOR MODULE
It is an object to provide a power semiconductor module having a case shared for base plates of different sizes and having a high-stability base plate. The...
METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE
A method for forming a semiconductor device structure is provided. The method includes performing a first process over a surface of a semiconductor substrate....
Semiconductor Packaging Having Warpage Control and Methods of Forming Same
An embodiment method for forming a semiconductor device package comprises bonding a first die to a package substrate and forming a molding compound over the...
WIRING BOARD AND SEMICONDUCTOR PACKAGE
A wiring board includes a substrate having first and second opposite surfaces, a first adhesive layer on the first surface of the substrate, a thermal...
A semiconductor device includes: a resin case that houses a semiconductor element; a parallel plate that is disposed inside the resin case while being...
MEASURING INDIVIDUAL LAYER THICKNESS DURING MULTI-LAYER DEPOSITION
In situ wafer metrology is conducted to reliably obtain deposition thickness for each successive layer in a multi-layer deposition. A wafer to be processed is...
METHOD OF FORMING A TEST STRUCTURE FOR DETECTING BAD PATTERNS, AND METHOD
OF DETECTING BAD PATTERNS USING THE SAME
A method of forming a test structure for detecting bad patterns includes classifying patterns in a chip into a plurality of groups, designing a layout of...
METHOD OF EVALUATING EPITAXIAL WAFER
The method of evaluating an epitaxial wafer includes performing evaluation of an epitaxial wafer by detecting, as a light point defect, an abnormal substance...
PROCESS FOR FABRICATING SOI TRANSISTORS FOR AN INCREASED INTEGRATION
A process for fabricating field-effect transistors, including providing a first semiconductor band surmounted with a first semiconductor layer; providing a...
SPACER SHAPER FORMATION WITH CONFORMAL DIELECTRIC FILM FOR VOID FREE PMD
An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop...
PUNCH-THROUGH-STOP AFTER PARTIAL FIN ETCH
A method of reducing current leakage in three-dimensional semiconductor devices due to short-channel effects includes providing a starting semiconductor...
SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES
A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method...
METHOD OF FORMING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE
The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which...
METHOD FOR PROCESSING A CARRIER
A method for processing a carrier may include: forming a plurality of structure elements at least one of over and in a carrier, wherein at least two adjacent...
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device may include forming a sacrificial layer on a substrate including a first region and a second region, forming a...
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A semiconductor device fabrication method includes sequentially forming a hard mask layer and a sacrificial layer on a substrate, forming an upper mandrel...
METHOD FOR THE REUSE OF GALLIUM NITRIDE EPITAXIAL SUBSTRATES
A method for the reuse of gallium nitride (GaN) epitaxial substrates uses band-gap-selective photoelectrochemical (PEC) etching to remove one or more epitaxial...
METHOD FOR MANUFACTURING A SILICON CARBIDE WAFER AND RESPECTIVE EQUIPMENT
An embodiment described herein includes a method for producing a wafer of a first semiconductor material. Said first semiconductor material has a first melting...
SEMICONDUCTOR SUBSTRATES, SEMICONDUCTOR PACKAGES AND PROCESSES OF MAKING
The present disclosure relates to semiconductor substrates useful in semiconductor packages. In an embodiment, a semiconductor substrate comprises a patterned...
RELIABLE PACKAGING AND INTERCONNECT STRUCTURES
Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an...
DIRECT PLASMA DENSIFICATION PROCESS AND SEMICONDUCTOR DEVICES
An aspect of the present disclosure relates to a method of forming a barrier layer on a semiconductor device. The method includes placing a substrate into a...
SELF-FORMING, SELF-ALIGNED BARRIERS FOR BACK-END INTERCONNECTS AND METHODS
OF MAKING SAME
Processes of forming an insulated wire into an interlayer dielectric layer (ILD) of a back-end metallization includes thermally treating a metallic barrier...
Patterning Method For Low-K Inter-Metal Dielectrics And Associated
Semiconductor fabrication techniques and associated semiconductor devices are provided in which conductive lines are separated by a low dielectric constant...
SELF-FORMING METAL BARRIERS
A technique includes applying a liquid dielectric composition onto a substrate, where the composition includes metal ions, at least partially curing the...
Interconnect Structures and Methods of Forming Same
An embodiment semiconductor device includes a first conductive feature in a dielectric layer and a second conductive feature over the dielectric layer and...
Method for Manufacturing a Semiconductor Substrate
A method for manufacturing a semiconductor substrate includes providing a first wafer having a first surface and a second surface opposite the first surface,...
METHOD OF FORMING INTER-LEVEL DIELECTRIC STRUCTURES ON SEMICONDUCTOR
A semiconductor device and a method for making the semiconductor device are provided. The method of making the semiconductor device may include patterning a...
REDUCTION OF BACKSIDE PARTICLE INDUCED OUT-OF-PLANE DISTORTIONS IN
A pin mechanism and a method for reducing backside particle induced out-of-plane distortions in semiconductor wafers involving such pin mechanisms. Geometric...
WORKPIECE CUTTING METHOD
A workpiece cutting method is provided. The workpiece cutting method includes an attaching step of attaching an adhesive tape to the front side or back side of...
Fan-Out Interconnect Structure and Methods Forming the Same
A method includes forming an adhesive layer over a carrier, forming a sacrificial layer over the adhesive layer, forming through-vias over the sacrificial...