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Patent # Description
2016/0307637 SONOS Byte-Erasable EEPROM
A SONOS byte-erasable EEPROM is disclosed. In one aspect, an apparatus includes a plurality of SONOS memory cells forming an EEPROM memory array. The apparatus...
2016/0307636 METHOD AND APPARATUS FOR IMPROVING DATA RETENTION AND READ-PERFORMANCE OF A NON-VOLATILE MEMORY DEVICE
Methods and apparatuses are contemplated herein for enhancing the read performance and data retention of nonvolatile memory devices. In an example embodiment,...
2016/0307635 STORAGE DEVICE AND RELIABILITY VERIFICATION METHOD
A method controlling the execution of a reliability verification operation in a storage device including a nonvolatile memory device includes; determining...
2016/0307634 CENTRALIZED VARIABLE RATE SERIALIZER AND DESERIALIZER FOR BAD COLUMN MANAGEMENT
A memory circuit includes an array subdivided into multiple divisions, each connectable to a corresponding set of access circuitry. A serializer/deserializer...
2016/0307633 NONVOLATILE MEMORY DEVICES AND METHODS OF OPERATING THE SAME
Methods of operating a nonvolatile memory device include performing erase loops on a memory block using a first voltage, performing program loops on memory...
2016/0307632 SEMICONDUCTOR DEVICE INCLUDING CELL REGION STACKED ON PERIPHERAL REGION AND METHOD OF FABRICATING THE SAME
Provided are semiconductor devices including a peripheral region and a cell region stacked thereon and a method of fabricating the same. The semiconductor...
2016/0307631 MITIGATION OF DATA RETENTION DRIFT BY PROGRMMING NEIGHBORING MEMORY CELLS
A method includes, in a plurality of memory cells that share a common isolation layer and store in the common isolation layer quantities of electrical charge...
2016/0307630 NONVOLATILE MEMORY DEVICES AND METHODS OF PROGRAMMING AND READING NONVOLATILE MEMORY DEVICES
In a method of programming a nonvolatile memory device, a program operation is performed on a selected memory cell coupled to a selected word line in response...
2016/0307629 Non-volatile memory for high rewrite cycles application
A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a...
2016/0307628 MEMORY CIRCUITS USING A BLOCKING STATE
A memory circuit with blocking states. In one embodiment, the memory circuit includes a two non-volatile transistors connected in series. The input state of...
2016/0307627 METHOD FOR PROGRAMMING MEMORY DEVICE AND ASSOCIATED MEMORY DEVICE
A method for programming a memory device comprises the following steps: performing an interleaving programming, including: programming a first memory cell...
2016/0307626 APPARATUSES, MEMORIES, AND METHODS FOR ADDRESS DECODING AND SELECTING AN ACCESS LINE
Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address...
2016/0307625 ELECTRONIC DEVICE
An electronic device includes a semiconductor memory unit, which includes resistive memory cells; an access circuit to apply, during a write operation, a write...
2016/0307624 Method of Operating Incrementally Programmable Non-Volatile Memory
An array of programmable non-volatile devices, such as a nominal OTP cell, is operated such that a V.sub.t representing a particular binary logic state is...
2016/0307623 Method of Operating Incrementally Programmable Non-Volatile Memory
An array of programmable non-volatile devices, such as a nominal OTP cell, is operated such that a V.sub.t representing a particular binary logic state is...
2016/0307622 PROGRAMMING MEMORIES WITH MULTI-LEVEL PASS SIGNAL
Methods of operating a memory include applying a multi-step pass voltage to a plurality of memory cells selected for a programming operation, applying a...
2016/0307621 Integrated Circuit With Separate Supply Voltage For Memory That Is Different From Logic Circuit Supply Voltage
In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the...
2016/0307620 SYSTEMS AND METHODS TO REFRESH DRAM BASED ON TEMPERATURE AND BASED ON CALIBRATION DATA
A system and method of refreshing dynamic random access memory (DRAM) are disclosed. A device includes a DRAM, a bus, and a system-on-chip (SOC) coupled via...
2016/0307619 SMART IN-MODULE REFRESH FOR DRAM
A dynamic Random Access Memory (DRAM) module (105) is disclosed. The DRAM module (105) can includes a plurality of banks (205-1, 205-2, 205-3, 205-4) to store...
2016/0307618 SENSE AMPLIFIER AND SEMICONDUCTOR DEVICE FOR SECURING OPERATION MARGIN OF SENSE AMPLIFIER
A sense amplifier includes an equalization unit configured to precharge a pair of bit lines to a level of a bit line precharge voltage in response to a bit...
2016/0307617 MEMORY DEVICES, SYSTEMS AND METHODS EMPLOYING COMMAND/ADDRESS CALIBRATION
During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test...
2016/0307616 SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS
A semiconductor device may include a power control signal generator and a sense amplifier circuit. The power control signal generator may generate a first...
2016/0307615 SELF-REFERENCED READ WITH OFFSET CURRENT IN A MEMORY
Self-referenced reading of a memory cell in a memory includes first applying a read voltage across the memory cell to produce a sample voltage. After applying...
2016/0307614 SEMICONDUCTOR APPARATUS
A semiconductor apparatus may include: a data storage group including first to eight data storage areas; a first channel select pad configured to transmit a...
2016/0307613 CIRCUITS FOR CONTROL OF TIME FOR READ OPERATION
A circuit for control of time for read operation is disclosed which additionally incorporates a dummy device circuit and a dummy sensitive amplifier circuit,...
2016/0307612 HIGH SPEED FPGA BOOT-UP THROUGH CONCURRENT MULTI-FRAME CONFIGURATION SCHEME
Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant...
2016/0307611 Memory Device with Internal Combination Logic
Embodiments of the present invention include an apparatus, method, and system for integrating data processing logic with memory. An embodiment of a memory...
2016/0307610 MEMORY SYSTEM THAT DETECTS BIT ERRORS DUE TO READ DISTURBANCE AND METHODS THEREOF
Methods and memory systems are provided that can detect bit errors due to read disturbances. A main page of a flash memory in a memory system is read. A bit...
2016/0307609 MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION
Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption....
2016/0307608 METHOD AND APPARATUS FOR CONTROLLING CURRENT IN AN ARRAY CELL
A method and an apparatus for controlling current in an array cell is disclosed. The method includes applying a supply voltage to a first access point of a...
2016/0307607 SEMICONDUCTOR DEVICE
To stably control a threshold voltage of a functional circuit using an oxide semiconductor. A variable bias circuit, a monitoring oxide semiconductor...
2016/0307606 Metallically Sealed, Wrapped Hard Disk Drives and Related Methods
Hard disk drives of the invention are wrapped in wraps for enhanced sealing of the hard disk drive. Wrapped hard disk drives of the invention comprise: an...
2016/0307605 METHOD, DEVICE, AND SYSTEM OF SYNCHRONOUSLY PLAYING MEDIA FILE
The present disclosure proposes a method of synchronously playing media file. The method includes: receiving, with a mobile terminal, parameter information...
2016/0307604 INTERFACE APPARATUS FOR DESIGNATING LINK DESTINATION, INTERFACE APPARATUS FOR VIEWER, AND COMPUTER PROGRAM
An interface apparatus for designating a link destination, is provided with: a range designating device (110) for designating a desired range in a screen on...
2016/0307603 INFORMATION PROCESSING DEVICE, INFORMATION RECORDING MEDIUM, INFORMATION PROCESSING METHOD, AND PROGRAM
There is provided an information processing device including: a data processing unit configured to execute a playback process of playing back data recorded on...
2016/0307602 METHODS AND APPARATUSES FOR PROCESSING OR DEFINING LUMINANCE/COLOR REGIMES
To allow a better coordination between an image creation artist such as a movie director of photography and the final viewer, via a receiving-side display and...
2016/0307601 IMAGE CONTROL DEVICE, IMAGE CONTROL SYSTEM, AND DIGITAL CAMERA
The invention is provided with: an acquisition unit that acquires, from an external machine, image data as well as time data when an image based on the image...
2016/0307600 CASE VIDEO PROCESSING APPARATUS, CASE VIDEO PROCESSING SYSTEM, AND CASE VIDEO PROCESSING METHOD
A video input unit inputs case video data to be processed, a face detector detects a face region of a person included in an image of video data, a target...
2016/0307599 Methods and Systems for Creating, Combining, and Sharing Time-Constrained Videos
A method of attributing contribution to a creation of time-constrained video content, includes: identifying a combination of content included in a...
2016/0307598 AUTOMATED EDITING OF VIDEO RECORDINGS IN ORDER TO PRODUCE A SUMMARIZED VIDEO RECORDING
One or more video cameras are used in conjunction with one or more data acquisition devices to record video and other data with a relationship to the video,...
2016/0307597 CASE VIDEO LOG DATA GENERATING APPARATUS, CASE VIDEO PROCESSING SYSTEM, AND CASE VIDEO LOG DATA GENERATING METHOD
A log generator generates log data including a processing time and processing contents, as data indicating a history of each of processes including input of...
2016/0307596 APPARATUS AND METHODS FOR THUMBNAIL GENERATION
Apparatus and methods for thumbnail generation. In one embodiment, a thumbnail stream is generated where one or more bits are assigned to key frames and...
2016/0307595 POST-WRITE SCAN OPERATIONS FOR INTERLACED MAGNETIC RECORDING
A storage device includes a data degradation management module that tracks a risk of data degradation by incrementing a track write counter of a first data...
2016/0307594 MAGNETIC DISK DEVICE AND METHOD OF CONTROLLING MAGNETIC DISK
According to one embodiment, a controller of a magnetic disk device is configured to manage a first value representing the number of times of writing for each...
2016/0307593 METHOD OF PLAYING SYSTEM STREAM FILES WITH DIFFERENT RECORDING FORMATS
In a playback method of a playback device that plays a system stream file including encrypted video information, the system stream file includes a first...
2016/0307592 PLASMON GENERATOR INCLUDING A MAIN BODY AND A FRONT PROTRUSION
A plasmon generator includes a main body, and a front protrusion protruding from the main body. The front protrusion has a proximal portion which is a boundary...
2016/0307591 Optical Information Reproduction Device and Optical Information Reproduction Method
Provided are an optical information reproduction device and a method therefor with which the influence of reference light reflected from the surface of a disk...
2016/0307590 ADAPTIVE LASER OUTPUT CONTROL IN A HAMR DEVICE
A current temperature of a data storage device having a heat assisted recording (HAMR) device is measured while in idle. A threshold laser diode power output...
2016/0307589 HOLOGRAM RECORDING AND PLAYBACK DEVICE AND PLAYBACK POSITION DEVIATION DETECTION METHOD
A hologram recording and playback device and a playback position deviation detection method to detect the relative position deviation between the hologram and...
2016/0307588 HGA LOADER WITH OPTICAL ALIGNMENT FOR AUTOMATED MAGNETIC HEAD TESTING
An HGA loader provides HGAs, in succession, to a multiple workstation head tester. An HGAs carrier station receives HGAs to be tested. An alignment station on...
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