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Patent # Description
2016/0315057 Reinforcement Structure and Method for Controlling Warpage of Chip Mounted on Substrate
A semiconductor device comprises a substrate, a die mounted on the substrate, a reinforcement plate bonded to the die, and an adhesive layer coupling the...
2016/0315056 PREVENTING UNAUTHORIZED USE OF INTEGRATED CIRCUITS FOR RADIATION-HARD APPLICATIONS
An integrated circuit, a method of forming an integrated circuit, and a semiconductor are disclosed for preventing unauthorized use in radiation-hard...
2016/0315055 INTEGRATED CIRCUIT STACK INCLUDING A PATTERNED ARRAY OF ELECTRICALLY CONDUCTIVE PILLARS
The present disclosure describes a stacked integrated circuit system that includes two integrated circuit layers stacked on opposite sides of an interposer...
2016/0315054 SEMICONDUCTOR DEVICE
A scale-like portion wherein metal plating is changed into a scale-like form is provided by continuously carrying out laser spot irradiation on a lead frame,...
2016/0315053 FLEXIBLE CRSS ADJUSTMENT IN A SGT MOSFET TO SMOOTH WAVEFORMS AND TO AVOID EMI IN DC-DC APPLICATION
A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate...
2016/0315052 SEMICONDUCTOR DEVICE HAVING CONDUCTIVE VIA AND MANUFACTURING PROCESS FOR SAME
In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package...
2016/0315051 SEMICONDUCTOR PACKAGE MANUFACTURING METHOD
The present disclosure provides a manufacturing method of a semiconductor packaging, including forming a redistribution layer (RDL) on a carrier, defining an...
2016/0315050 CAPACITOR WITH FUSE PROTECTION
An embodiment is a circuit. The circuit includes active circuitry, a first capacitor, a first fuse, a second capacitor, and a second fuse. The active circuitry...
2016/0315049 METHOD AND STRUCTURE OF FORMING FINFET ELECTRICAL FUSE STRUCTURE
An e-Fuse structure is provided on a surface of an insulator layer of a semiconductor-on-insulator substrate (SOI). The e-Fuse structure includes a first metal...
2016/0315048 SEMICONDUCTOR ELECTROPLATING SYSTEM
A semiconductor electroplating system includes a conducting ring and at least one conductive device. The conducting ring is used for carrying a wafer. The...
2016/0315047 MICROELECTRONIC COMPONENTS WITH FEATURES WRAPPING AROUND PROTRUSIONS OF CONDUCTIVE VIAS PROTRUDING FROM...
In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A,...
2016/0315046 METHOD OF FORMING HIGH DENSITY, HIGH SHORTING MARGIN, AND LOW CAPACITANCE INTERCONNECTS BY ALTERNATING RECESSED...
Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According...
2016/0315045 SEMICONDUCTOR DEVICES INCLUDING A CONTACT STRUCTURE AND METHODS OF MANUFACTURING THE SAME
The semiconductor device may include an insulating interlayer on the substrate, the substrate including a contact region at an upper portion thereof, a main...
2016/0315044 ELECTRONIC DEVICE PACKAGE, ELECTRONIC DEVICE STRUCTURE AND METHOD OF FABRICATING ELECTRONIC DEVICE PACKAGE
According to embodiments of the disclosure, an electronic device package may include a wire layer and a rigid element. The wire layer includes a first surface...
2016/0315043 CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
A chip package includes a chip, an isolation layer, and a redistribution layer. The chip has a substrate, an electrical pad, and a protection layer. The...
2016/0315042 PRINTED CIRCUIT BOARD, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Disclosed is a printed circuit board including an insulating layer, a circuit layer formed on a lower surface of the insulating layer, and a metal post...
2016/0315041 DOUBLE SIDE VIA LAST METHOD FOR DOUBLE EMBEDDED PATTERNED SUBSTRATE
An interposer substrate includes a first circuit pattern embedded at a first surface of a dielectric layer and a second circuit pattern embedded at a second...
2016/0315040 CORE FOR REVERSE REFLOW, SEMICONDUCTOR PACKAGE, AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE
Provided are a reverse-reflow core, a semiconductor package, and a method of fabricating a semiconductor package. The semiconductor package includes: a...
2016/0315039 Hybrid Packaged Lead Frame Based Multi-Chip Semiconductor Device with Multiple Interconnecting Structures
A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first ...
2016/0315038 SEMICONDUCTOR MODULE
A semiconductor module including a circuit block that has an electrically insulating layer, a plurality of circuit patterns formed on one surface of the...
2016/0315037 SEMICONDUCTOR DEVICE
A semiconductor device includes a first switching element; a second switching element; a first metal member; a second metal member; a first terminal that has a...
2016/0315036 DUAL TRANSISTORS FABRICATED ON LEAD FRAMES AND METHOD OF FABRICATION
A dual transistor device includes a first transistor having a first drain, a first gate, and first source and a second transistor having a second drain, a...
2016/0315035 METHOD OF PRODUCING LEAD FRAMES FOR ELECTRONIC COMPONENTS, CORRESPONDING COMPONENT AND COMPUTER PROGRAM PRODUCT
An electronic component, such as an integrated circuit, includes at least one circuit having coupled therewith electrical connections including a lead frame of...
2016/0315034 METHOD OF PRODUCING ELECTRONIC COMPONENTS, CORRESPONDING COMPONENT AND COMPUTER PROGRAM PRODUCT
An electronic component includes one or more circuits having electrical connections coupled therewith. The electrical connections include a lead frame as well...
2016/0315033 Device Including a Logic Semiconductor Chip Having a Contact Electrode for Clip Bonding
A device includes a logic semiconductor chip having a contact electrode. The contact electrode is configured to be electrically coupled to a contact clip based...
2016/0315032 SEMICONDUCTOR DEVICES AND METHODS OF MAKING THE SAME
In one embodiment, methods for making semiconductor devices are disclosed.
2016/0315031 LEAD BONDING STRUCTURE
A lead bonding structure includes: a plurality of leads extending outward from a package; and a plurality of electrode pads formed on a circuit board. The...
2016/0315030 REUSABLE THERMOPLASTIC THERMAL INTERFACE MATERIALS AND METHODS FOR ESTABLISHING THERMAL JOINTS BETWEEN HEAT...
According to various aspects, exemplary embodiments are disclosed of thermal interface materials, electronic devices, and methods for establishing thermal...
2016/0315029 SEMICONDUCTOR PACKAGE AND THREE-DIMENSIONAL SEMICONDUCTOR PACKAGE INCLUDING THE SAME
There is provided a semiconductor package including: a semiconductor chip; and an extension die provided on the semiconductor chip, wherein the semiconductor...
2016/0315028 MULTI-CHIP PACKAGE STRUCTURE, WAFER LEVEL CHIP PACKAGE STRUCTURE AND MANUFACTURING PROCESS THEREOF
A multi-chip package structure includes a first chip, a second chip, a circuit layer, a plurality of first conductive bumps, a plurality of second conductive...
2016/0315027 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
A semiconductor package and manufacturing method thereof includes a chip member installed on an upper surface, a lower surface, or both of a substrate. The...
2016/0315026 CURED PRODUCT
The present application relates to a cured product and the use thereof. When the cured product, for example, is applied to a semiconductor device such as an...
2016/0315025 RESIN COMPOSITION, RESIN FILM, SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF
A film-forming resin composition for use in encapsulating large-diameter thin-film wafers includes (A) a silicone resin having a weight-average molecular...
2016/0315024 MECHANICAL HANDLING SUPPORT FOR THIN CORES USING PHOTO-PATTERNABLE MATERIAL
An integrated circuit package includes a core such as a thin glass core with through-core vias. A photo-patternable material is disposed directly on surfaces...
2016/0315023 SEMICONDUCTOR DEVICE
A first conductor layer is provided on a first surface of an insulating plate, and has a first volume. A second conductor layer is provided on a second surface...
2016/0315022 POWER SEMICONDUCTOR DEVICE
This invention is provided with: a circuit board which is placed in a package and in which an electric circuit including a power semiconductor element is...
2016/0315021 METHODS FOR SHIELDING A PLASMA ETCHER ELECTRODE
Methods for plasma etching are disclosed. In one embodiment, a method of etching a plurality of features on a wafer includes positioning a wafer on a feature...
2016/0315020 SILICON SINGLE CRYSTAL WAFER, MANUFACTURING METHOD THEREOF AND METHOD OF DETECTING DEFECTS
A silicon single crystal wafer is provided. The silicon single crystal wafer includes an IDP which is divided into an NiG region and an NIDP region, wherein...
2016/0315019 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING A COMPOSITION FOR REMOVING PHOTORESIST AND METHODS OF...
A composition for removing photoresist, including an alkyl ammonium fluoride salt in an amount ranging from about 0.5 weight percent to about 10 weight...
2016/0315018 METHODS OF FABRICATING FINFET SEMICONDUCTOR DEVICES INCLUDING DUMMY STRUCTURES
Provided are a semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a first active fin and a second...
2016/0315017 SEMICONDUCTOR DEVICE HAVING GATE-ALL-AROUND TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a fin structure disposed on a substrate, a sacrificial layer pattern disposed on the fin structure, an active layer pattern...
2016/0315016 METHOD OF MANUFACTURING P-CHANNEL FET DEVICE WITH SIGE CHANNEL
A method of forming a semiconductor device is provided including providing a semiconductor-on-insulator (SOI) wafer comprising a first semiconductor layer...
2016/0315015 Voids in STI Regions for Forming Bulk FinFETs
An embodiment is an integrated circuit structure including two insulation regions over a substrate with one of the two insulation regions including a void, at...
2016/0315014 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A method for manufacturing a semiconductor structure is provided. A plurality of trenches are formed in a substrate. The trenches define at least one fin...
2016/0315013 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Object is to provide a semiconductor device having improved reliability or performance. A high-breakdown-voltage n type transistor has source and drain regions ...
2016/0315012 Method of detaching semiconductor material from a carrier and device for performing the method
Various embodiments provide a method of detaching semiconductor material from a carrier, wherein the method comprises providing a carrier having attached...
2016/0315011 WAFER PROCESSING METHOD
Disclosed herein is a wafer processing method for dividing a wafer into a plurality of individual devices along a plurality of crossing division lines. The...
2016/0315010 METHOD AND DEVICE FOR CUTTING WAFERS
A method is described of radiatively cutting a wafer, the method comprising the steps of low power cutting of two trenches followed by high power cutting of a...
2016/0315009 UV-CURE PRE-TREATMENT OF CARRIER FILM FOR WAFER DICING USING HYBRID LASER SCRIBING AND PLASMA ETCH APPROACH
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor...
2016/0315008 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor structure, a plurality of gate structures, at least one source/drain structure, at least one trench, a...
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