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Patent # Description
2016/0314857 LOCALISED ENERGY CONCENTRATION
There is provided a method of producing a localised concentration of energy. The method includes creating at least one shockwave propagating through a...
2016/0314856 SPONTANEOUS ALPHA PARTICLE EMITTING METAL ALLOYS AND METHOD FOR REACTION OF DEUTERIDES
This invention describes materials and apparatuses suitable for triggering a low energy nuclear reaction of deuterium nuclei in a metal alloy consisting of a...
2016/0314855 SYSTEMS AND METHODS FOR COMPRESSING PLASMA
Embodiments of systems and methods for compressing plasma are described in which plasma pressures above the breaking point of solid material can be achieved by...
2016/0314854 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME
A semiconductor memory device includes a memory cell array having a first group of main blocks, a second group of main blocks and redundancy blocks replacing...
2016/0314853 METHOD AND APPARATUS FOR IDENTIFYING ERRONEOUS DATA IN AT LEAST ONE MEMORY ELEMENT
A method for identifying erroneous data in at least one memory element, particularly a register, that includes at least one flip-flop that is intended to allow...
2016/0314852 SYSTEM AND METHOD OF MEMORY MANAGEMENT
Embodiments of system and methods for managing memory cells are disclosed, where a memory priority map is generated based on at least one testing procedure,...
2016/0314851 PULSE SIGNAL OUTPUT CIRCUIT AND SHIFT REGISTER
An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse...
2016/0314850 SHIFT REGISTER UNIT, METHOD FOR DRIVING THE SAME, GATE DRIVER CIRCUIT AND DISPLAY DEVICE
The present disclosure provides a shift register unit, its driving method, a gate driver circuit and a display device. The shift register unit includes an...
2016/0314849 MEMORY DEVICE AND READING METHOD THEREOF
A memory device includes: a plurality of conductive stacked structures including at least a string select line, a plurality of word lines and at least a ground...
2016/0314848 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device has a memory block including memory strings with first and second selection transistors at opposite ends of the memory strings. A...
2016/0314847 ADAPTIVE BLOCK PARAMETERS
Data programmed in a block using a first set of programming parameters is read and a number of memory cells having threshold voltages in an intermediate...
2016/0314846 COMMON SOURCE ARCHITECTURE FOR SPLIT GATE MEMORY
A memory system has an array of split gate non-volatile NVM cells that are in program sectors and the program sectors make up one or more erase sectors. The...
2016/0314845 Method for determining an optimal voltage pulse for programming a flash memory cell
A method for determining an optimal voltage pulse for programming a flash memory cell, the optimal voltage pulse being defined by a voltage ramp from a...
2016/0314844 NATURAL THRESHOLD VOLTAGE COMPACTION WITH DUAL PULSE PROGRAM FOR NON-VOLATILE MEMORY
A control circuit, in communication with non-volatile memory cells, is configured to distinguish and classify the memory cells into the different subsets of...
2016/0314843 Non-Volatile Memory With Two Phased Programming
Programming non-volatile memory includes applying a series of programming pulses to the memory cells as part of a coarse/fine programming process. Between...
2016/0314842 MEMORY SYSTEM AND OPERATING METHOD THEREOF
A memory system includes: a memory device comprising at least a page; and a controller suitable for setting a seed offset according to a size of a restricted...
2016/0314841 HIGH PERFORMANCE DIGITAL TO ANALOG CONVERTER
A digital-to-analog converter (DAC) may include a conversion block providing a first analog value. The DAC may also include an amplification block for...
2016/0314840 THREE-DIMENSIONAL NONVOLATILE MEMORY AND RELATED READ METHOD DESIGNED TO REDUCE READ DISTURBANCE
A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to...
2016/0314839 Dual Function Hybrid Memory Cell
A dual function hybrid memory cell is disclosed. In one aspect, the memory cell includes a substrate, a bottom charge-trapping region formed on the substrate,...
2016/0314838 APPARATUS TO REDUCE RETENTION FAILURE IN COMPLEMENTARY RESISTIVE MEMORY
Described is an apparatus which comprises: a complementary resistive memory bit-cell; and a sense amplifier coupled to the complementary resistive memory...
2016/0314837 SYSTEM FOR WRITING DATA IN A MEMORY
A system including: a first memory including several portions of one or more pages each, said memory including first and second ports that can simultaneously...
2016/0314836 REFERENCE VOLTAGE GENERATION APPARATUSES AND METHODS
A method and apparatuses for generating a reference voltage are disclosed. One example apparatus includes a current source coupled to a first power supply. The...
2016/0314835 ELECTRONIC DEVICE AND METHOD FOR OPERATING ELECTRONIC DEVICE
An electronic device comprising a semiconductor memory unit that may a variable resistance element configured to be changed in its resistance value in response...
2016/0314834 Rewritable Multibit Non-Volatile Memory With Soft Decode Optimization
A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit...
2016/0314833 PARTIAL/FULL ARRAY/BLOCK ERASE FOR 2D/3D HIERARCHICAL NAND
A novel 2D/3D hierarchical-BL NAND array with at least one plane on independent Psubstrate comprising a plurality of LG groups respectively associated with a...
2016/0314832 Circuits and Methods for Performance Optimization of SRAM Memory
In described examples, a memory controller circuit controls accesses to an SRAM circuit. Precharge mode control circuitry outputs: a burst mode enable signal...
2016/0314831 INTEGRATED CIRCUIT CHIP HAVING TWO TYPES OF MEMORY CELLS
An integrated circuit chip includes a first type memory cell and a second type memory cell. The first type memory cell includes a first reference line landing...
2016/0314830 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device may include: a plurality of banks suitable for performing an all bank refresh operation or single bank refresh operation; an...
2016/0314829 INTEGRATED CIRCUIT
An integrated circuit device comprises a first data processing element having a first data interface configured to synchronously communicate data according to...
2016/0314828 FAST PROGRAMMING OF MAGNETIC RANDOM ACCESS MEMORY (MRAM)
A method of programming an MTJ includes selecting an MTJ that is coupled to an access transistor at the drain of the access transistor. The gate of the access...
2016/0314827 A Memory Device, Comprising at Least One Element and Associated Method Spintronics
A storage device, comprising at least one spintronic element suitable for representing a state among at least n states associated with the spintronic element,...
2016/0314826 BITCELL STATE RETENTION
In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access...
2016/0314825 PERPENDICULAR MAGNETIZATION FILM, PERPENDICULAR MAGNETIZATION FILM STRUCTURE, MAGNETORESISTANCE ELEMENT, AND...
Provided is a structure having a perpendicular magnetization film which is an (Mn.sub.1-x,Ga.sub.x).sub.4N.sub.1-y (0<x.ltoreq.0.5, 0<y<1) thin film...
2016/0314824 APPARATUSES AND METHODS FOR PROVIDING ACTIVE AND INACTIVE CLOCK SIGNALS TO A COMMAND PATH CIRCUIT
Apparatuses and methods for providing active and inactive clock signals to a command path circuit are described. An example method includes providing an active...
2016/0314823 METHODS AND APPARATUSES FOR COMMAND SHIFTER REDUCTION
Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit,...
2016/0314822 TRAINING AND OPERATIONS WITH A DOUBLE BUFFERED MEMORY TOPOLOGY
System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight...
2016/0314821 METHOD FOR ACCESSING MULTI-PORT MEMORY MODULE, METHOD FOR INCREASING WRITE PORTS OF MEMORY MODULE AND...
A method for accessing a multi-port memory module comprising a plurality of banks is provided, wherein the plurality of banks comprise at least a first bank, a...
2016/0314820 MEMORY ELEMENTS AND CROSS POINT SWITCHES AND ARRAYS OF SAME USING NONVOLATILE NANOTUBE BLOCKS
Under one aspect, a covered nanotube switch includes: (a) a nanotube element including an unaligned plurality of nanotubes, the nanotube element having a top...
2016/0314819 SYSTEMS AND METHODS OF THUMBNAIL GENERATION
A method includes receiving a plurality of images at an encoder device and encoding the plurality of encoder images to generate an output video stream, where...
2016/0314818 METHOD AND DEVICE FOR ASSOCIATING FRAMES IN A VIDEO OF AN ACTIVITY OF A PERSON WITH AN EVENT
Described are methods and systems for associating frames in a video of an activity of a person with an event. The methods include recording a video of an...
2016/0314817 DESIGNATING PARTIAL RECORDINGS AS PERSONALIZED MULTIMEDIA CLIPS
Methods, systems, and computer readable media may be operable to facilitate the creation of personalized partial recordings of multimedia content. A partial...
2016/0314816 AUTOMATIC PLAYBACK OVERSHOOT CORRECTION SYSTEM
An automatic playback overshoot correction system predicts the position in the program material where the user expects to be when the user stops the fast...
2016/0314815 Data Storage Component Testing System
A testing system that is capable of testing individual data storage components may have testing, loader, and exchange assemblies with the testing assembly...
2016/0314814 Systems and Methods for Side-Track Aided Data Recovery
Embodiments of the present inventions are related to systems and methods for data processing, and more particularly to systems and methods for reducing...
2016/0314813 DATA STORAGE COMPONENT TEST DECK SYSTEM
A system may utilize at least an enclosed test deck that has an access port door covering an access port. The system can test a data storage component by...
2016/0314812 OPTICAL INFORMATION RECORDING MEDIUM AND REPRODUCTION METHOD
In a case where (i) a reflectance calculated from a reflected light amount obtained from a longest pit (P1max) or a longest space (S1max) in a first pit row is...
2016/0314811 ONSET LAYER FOR PERPENDICULAR MAGNETIC RECORDING MEDIA
A magnetic storage medium according to one embodiment includes a substrate; an onset layer formed above the substrate, the onset layer comprising ruthenium and...
2016/0314810 WRITER POLE FORMATION
Implementations disclosed herein provide a method of reducing the topography at the alignment and overlay marks area during the writer pole photolithography...
2016/0314809 MAGNETIC RECORDING HEAD AND DISK DEVICE WITH THE SAME
According to one embodiment, a magnetic recording head includes an air bearing surface, a magnetic pole having a distal end portion, a write shield opposed to...
2016/0314808 HEAD ACTUATOR ASSEMBLY, FLEXIBLE PRINTED CIRCUIT UNIT, AND DISK DRIVE WITH THE SAME
A head actuator assembly includes a carriage assembly including a bearing portion, first and second suspension assemblies extending from the bearing portion...
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