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Patent # Description
2016/0322408 LAYOUT FOR ROUTING COMMON SIGNALS TO INTEGRATING IMAGING PIXELS
An imager is provided that includes an integrated circuit. The integrated circuit includes at least one metal layer, a signal line extending in a first...
2016/0322407 Image Sensor Pickup Region Layout
Embodiments of the present disclosure include an image sensor device and methods of forming the same. An embodiment is an image sensor device including a first...
2016/0322406 PHOTOELECTRIC CONVERSION APPARATUS AND IMAGING SYSTEM USING THE SAME
In a photoelectric conversion apparatus including charge storing portions in its imaging region, isolation regions for the charge storing portions include...
2016/0322405 LIGHT DETECTION DEVICE
A semiconductor light detection element has a plurality of channels, each of which consists of a photodiode array including a plurality of avalanche...
2016/0322404 METHODS FOR PRODUCING TFT ARRAY SUBSTRATE AND DISPLAY APPARATUS
Embodiments of the present disclosure provide a method for producing a TFT array substrate and a method for producing a display apparatus. The method for...
2016/0322403 Flexible Base Substrate and Fabrication Method Thereof
Embodiments of the present invention provide a flexible base substrate and a fabrication method thereof. The flexible base substrate comprises: a first...
2016/0322402 DISPLAY APPARATUS HAVING A STEPPED PART
Provided is a display apparatus including a substrate and a semiconductor layer including first and second semiconductor layers. A first gate insulating layer...
2016/0322401 GOA Unit and Method for Producing the Same, Gate Driver Circuit
Embodiments of the present disclosure provide a GOA unit and a method for producing the same and a gate driver circuit, which are directed to a field of...
2016/0322400 SEMICONDUCTOR ELEMENT AND DISPLAY DEVICE USING THE SAME
Provided is a semiconductor element including: a semiconductor having an active layer; a gate insulating film which is in contact with the semiconductor; a...
2016/0322399 DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF
A manufacturing method includes forming a gate member and a common electrode line on a substrate. A gate insulating layer is formed on the gate member and the...
2016/0322398 PIXEL UNIT, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREFOR, DISPLAY PANEL AND DISPLAY DEVICE
Disclosed are a pixel unit, an array substrate and a manufacturing method therefor, a display panel and a display device. At least two step portions adjacent...
2016/0322397 DISPLAY SUBSTRATE AND METHOD OF REPAIRING DEFECTS THEREOF
A display substrate includes a gate metal pattern including a gate line extending in a first direction, a gate electrode electrically connected to the gate...
2016/0322396 ARRAY SUBSTRATE, ITS MANUFACTURING METHOD, DISPLAY PANEL AND DISPLAY DEVICE
The present disclosure provides an array substrate, its manufacturing method, a display panel and a display device. A conductive metal pattern of the array...
2016/0322395 SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF THE SAME, OR DISPLAY DEVICE INCLUDING THE SAME
To provide a novel semiconductor device including an oxide semiconductor film. The semiconductor device includes a first transistor and a second transistor....
2016/0322394 DISPLAY MOTHERBOARD, DISPLAY PANEL AND DISPLAY DEVICE
The invention provides a display motherboard, a display panel and a display device for solving the problem of unsmooth cutting of the display motherboard in...
2016/0322393 METHOD AND STRUCTURE FOR PREVENTING EPI MERGING IN EMBEDDED DYNAMIC RANDOM ACCESS MEMORY
After forming a plurality of first semiconductor fins having a first spacing in a logic device region and a plurality of second semiconductor fins having a...
2016/0322392 STRUCTURE HAVING GROUP III-V, Ge AND SiGe FINS ON INSULATOR
A method provides a first substrate supporting an insulator layer having trenches formed therein; filling the trenches using an epitaxial growth process with...
2016/0322391 METHOD OF FORMING FINS FROM DIFFERENT MATERIALS ON A SUBSTRATE
A method of forming fins of different materials includes providing a substrate with a layer of a first material having a top surface, masking a first portion...
2016/0322390 THIN FILM TRANSISTORS, METHODS OF MANUFACTURING THE SAME AND DISPLAY DEVICES INCLUDING THE SAME
A thin film transistor includes a gate electrode on a substrate, a gate insulation layer which covers the gate electrode on the substrate, an oxide...
2016/0322389 DISPLAY DEVICE
In a display device, a substrate has a pixel structure which has a first conductive layer, a second conductive layer and an oxide semiconductor layer. A trace...
2016/0322388 ARRAY SUBSTRATE, ITS MANUFACTURING METHOD AND DISPLAY DEVICE
The present disclosure provides an array substrate, its manufacturing method and a display device. The array substrate includes a gate electrode, a gate...
2016/0322387 DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF
A display device includes: a first substrate; a gate line on the first substrate; a gate electrode disposed on the first substrate and protruding from the gate...
2016/0322386 Method of Forming a Semiconductor Substrate With Buried Cavities and Dielectric Support Structures
A semiconductor device includes a semiconductor substrate with a first surface. The device further includes one or more semiconductor devices formed or the...
2016/0322385 SUBSTRATE BIAS FOR FIELD-EFFECT TRANSISTOR DEVICES
Substrate bias for field-effect transistor (FET) devices. In some embodiments, a radio-frequency (RF) device can include a FET implemented over a substrate...
2016/0322384 SEMICONDUCTOR STRUCTURE HAVING LOGIC REGION AND ANALOG REGION
A method can include epitaxially growing epitaxial growth material within a logic region of a semiconductor structure. A method can include performing...
2016/0322383 SEMICONDUCTOR DEVICE
A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact...
2016/0322382 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device includes forming on a lower structure, a first stack structure in which first material layers and second...
2016/0322381 MULTILEVEL MEMORY STACK STRUCTURE EMPLOYING SUPPORT PILLAR STRUCTURES
A first stack of alternating layers including first electrically insulating layers and first sacrificial material layers is formed with first stepped surfaces....
2016/0322380 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
According to an embodiment, a semiconductor memory device comprises a stacked body, a semiconductor layer, a charge accumulation layer, and a first layer. The...
2016/0322379 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, a charge accumulation layer,...
2016/0322378 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
According to an embodiment, a semiconductor memory device comprises a substrate, a plurality of control gate electrodes, a semiconductor layer, a charge...
2016/0322377 SEMICONDUCTOR MEMORY DEVICE
The memory string includes a plurality of control gate electrodes, a semiconductor layer, and an electric charge accumulating layer. The plurality of control...
2016/0322376 THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
Disclosed is a three-dimensional semiconductor device, including: a peripheral circuit; a memory cell array stacked on the peripheral circuit and including a...
2016/0322375 NON-VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
A non-volatile memory device includes a substrate having a first area and a second area around the first area, memory cells in the first area. Each memory cell...
2016/0322374 MULTIHEIGHT CONTACT VIA STRUCTURES FOR A MULTILEVEL INTERCONNECT STRUCTURE
A recessed region can be formed on a semiconductor substrate, and peripheral semiconductor devices can be formed on a recessed horizontal surface of the...
2016/0322373 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first...
2016/0322372 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes a substrate, a plurality of memory cells, a logic gate electrode and a high-voltage gate electrode. The substrate at least...
2016/0322371 Sidewall Assisted Process for Wide and Narrow Line Formation
A method of forming narrow and wide lines includes forming mandrels separated by wider gaps and narrower gaps, forming sidewall spacers on sides of the gaps,...
2016/0322370 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a substrate having a memory array region and a peripheral region, isolation layers formed in the peripheral region to define an...
2016/0322369 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
A nonvolatile semiconductor memory device includes first and second word line groups, each including a plurality of stacked word lines above a substrate, a...
2016/0322368 Three-Dimensional Ferroelectric FET-Based Structures
Exemplary embodiments of the present disclosure are directed to three-dimensional (3D) Ferroelectric-gated FET (FeFET) structures that can be used to implement...
2016/0322367 MEMORY BIT CELL FOR REDUCED LAYOUT AREA
An approach for providing SRAM bit cells with miniaturized bit cells, without local interconnection layers, with improved lithographic printability, and...
2016/0322366 STATIC RANDOM ACCESS MEMORY
A static random access memory (SRAM) is disclosed. The SRAM includes a plurality of SRAM cells on a substrate, in which each of the SRAM cells comprises: a...
2016/0322365 SEMICONDUCTOR DEVICE HAVING AIR GAP, A METHOD FOR MANUFACTURING THE SAME, A MEMORY CELL HAVING THE SAME AND AN...
A semiconductor device may include: a semiconductor substrate comprising a plurality of active regions and a device isolation region for isolating the...
2016/0322364 SEMICONDUCTOR DEVICE FOR REDUCING COUPLING CAPACITANCE
A semiconductor device includes a spacer having a nitride/oxide/nitride (NON) structure. The spacer is disposed between a sidewall of a bit line and a bit line...
2016/0322363 MEMORY CELLS HAVING A FOLDED DIGIT LINE ARCHITECTURE
Memory arrays having folded architectures and methods of making the same. Specifically, memory arrays having a portion of the transistors in a row that are...
2016/0322362 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES HAVING BURIED CONTACTS AND RELATED SEMICONDUCTOR DEVICES
A method of manufacturing a semiconductor device includes: forming bit line structures spaced apart from each other by first groove disposed in first...
2016/0322361 SEMICONDUCTOR DEVICE HAVING SUB-CELL BLOCKS
A semiconductor device includes a substrate with cell and peripheral regions and capacitors provided on the cell region. The cell region may include a...
2016/0322360 FLOATING BODY MEMORY CELL HAVING GATES FAVORING DIFFERENT CONDUCTIVITY TYPE REGIONS
A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is...
2016/0322359 SELECTIVE GERMANIUM P-CONTACT METALIZATION THROUGH TRENCH
Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be...
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