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REAR SURFACE-PROTECTIVE FILM, FILM, METHOD FOR PRODUCING SEMICONDUCTOR
DEVICE, AND METHOD FOR PRODUCING CHIP
Disclosed are a rear surface-protective film making it possible to detect, after this film is bonded to a semiconductor wafer, a notch in this wafer, and to...
METHOD OF FORMING MARK PATTERN, RECORDING MEDIUM AND METHOD OF GENERATING
In a method of forming a mark pattern according to the embodiments, a film to be processed on a substrate is coated with a photosensitive film, and the...
Integrated Circuit Substrate and Method for Manufacturing the Same
The description discloses a method for use in manufacturing integrated circuit chips. The method comprises providing a wafer having a plurality of integrated...
CHIP PACKAGE AND FABRICATION METHOD THEREOF
A chip package includes a chip, a laser stop layer, a first though hole, an isolation layer, a second though hole and a conductive layer. The laser stop layer...
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
A semiconductor device includes a gate structure extending in a second direction on a substrate, a source/drain layer disposed on a portion of the substrate...
Semiconductor devices and fabrication methods are provided. In a semiconductor device, a semiconductor substrate includes a first electrode layer having a top...
MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
According to one embodiment, a memory device includes a conductive member and a stacked body provided on the conductive member. The stacked body includes a...
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
A BPSG film (104) arranged on fuse elements (103), an interlayer insulating film (105) for laminating metal wiring, and a silicon nitride film (106) formed...
INTEGRATED DEVICE PACKAGE COMPRISING AN ELECTROMAGNETIC (EM) PASSIVE
DEVICE IN AN ENCAPSULATION LAYER, AND AN...
Some novel features pertain to an integrated device package that includes a die, an electromagnetic (EM) passive device, an encapsulation layer covering the...
A semiconductor device includes an opening, a metal nitride layer, a bilayer metal layer and a conductive bulk layer. The opening is disposed in a first...
CUT FIRST ALTERNATIVE FOR 2D SELF-ALIGNED VIA
A method of lithographically cutting a Mx line before the Mx line is lithographically defined by patterning and the resulting 2DSAV device are provided....
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device and a manufacturing method thereof are provided. A semiconductor device includes a stack structure including conductive layers stacked...
PACKAGE SUBSTRATES, SEMICONDUCTOR PACKAGES HAVING THE PACKAGE SUBSTRATES,
AND METHODS FOR FABRICATING THE...
Package substrates, semiconductor packages including the package substrates, and methods for fabricating the semiconductor packages are provided. A package...
A wiring substrate includes a first wiring substrate, a first insulation layer stacked on the first wiring layer, and second and third insulation layers...
A wiring substrate includes a first wiring substrate, a first insulation layer covering the first wiring layer, a second insulation layer stacked on the first...
PRINTED WIRING BOARD, METHOD FOR PRODUCING PRINTED WIRING BOARD AND
The present invention provides a printed wiring board comprising: a conductor circuit on an insulating substrate, a white solder resist layer which is composed...
SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR PROCESS
Disclosed is a semiconductor package structure and manufacturing method. The semiconductor package structure includes a first dielectric layer, a second...
WORK PIECES AND METHODS OF LASER DRILLING THROUGH HOLES IN SUBSTRATES
USING AN EXIT SACRIFICIAL COVER LAYER
Work pieces and methods of forming through holes in substrates are disclosed. In one embodiment, a method of forming a through hole in a substrate by drilling...
SUBSTRATE FOR INTEGRATED CIRCUIT DEVICES INCLUDING MULTI-LAYER GLASS CORE
AND METHODS OF MAKING THE SAME
Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers...
A wiring substrate includes a first wiring layer, a first insulation layer, and a second wiring layer. The first insulation layer covers an upper surface and a...
Fan-Out Wafer Level Package Structure
A method for forming a package structure may comprise applying a die and vias on a carrier having an adhesive layer and forming a molded substrate over the...
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE
A semiconductor device is disclosed in which an implant board and a semiconductor element of a semiconductor mounting board are bonded and electrically...
Semiconductor Device and Power Converter Using the Same
To suppress a temperature rise of a chip accompanying a production of large output by a power converter, and to reduce a size of the power converter. A power...
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device 100 includes a first insulating material 110 attached to a second main surface 106b of a semiconductor chip 106, and a second insulating...
METHOD OF TRANSFERRING AND ELECTRICALLY JOINING A HIGH DENSITY MULTILEVEL
THIN FILM TO A CIRCUITIZED AND...
A method is for making an electronic device and includes forming an interconnect layer stack on a sacrificial substrate and having a plurality of patterned...
ENCAPSULATED CONFORMAL ELECTRONIC SYSTEMS AND DEVICES, AND METHODS OF
MAKING AND USING THE SAME
Encapsulated conformal electronic devices, encapsulated conformal integrated circuit (IC) sensor systems, and methods of making and using encapsulated...
THROUGH ELECTRODE, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE
AND MANUFACTURING METHOD THEREOF
Provided are a through electrode including an organic side-wall insulating film, capable of eliminating a barrier layer and achieving satisfactory mechanical...
POWER MODULE AND METHOD FOR MANUFACTURING THE SAME
A power module or the like is provided in which lower inductance and miniaturization are achieved. The power module includes: main body units (11 to 13),...
PACKAGE FOR A SEMICONDUCTOR DEVICE
A package for a semiconductor device or circuit comprises a semiconductor switch module having a metallic base on an exterior side and metallic pads. A sealed...
PACKAGE FOR A SEMICONDUCTOR DEVICE
A package for a semiconductor device or circuit comprises a semiconductor switch module having a metallic base on an exterior side and metallic pads. A...
The present invention provides a semiconductor device that is reduced in size by changing the structure of a fixing portion used for fixing a semiconductor...
INTEGRATION OF BACKSIDE HEAT SPREADER FOR THERMAL MANAGEMENT
A microelectronic device includes semiconductor device with a component at a front surface of the semiconductor device and a backside heat spreader layer on a...
INTEGRATED CIRCUIT CHIP ASSEMBLED ON AN INTERPOSER
A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal...
COOLER-INTEGRATED SEMICONDUCTOR MODULE
A cooler-integrated semiconductor module, includes an insulating substrate; a circuit layer disposed on a front surface of the insulating substrate; a...
A semiconductor device includes a laminated substrate having circuit boards, an insulating plate, and a metal plate laminated, and warped convexly to the...
SIX-SIDED PROTECTION OF A WAFER-LEVEL CHIP SCALE PACKAGE (WLCSP)
Consistent with an example embodiment, a WLCSP (wafer-level chip-scale package) device may be encapsulating in a six-sided protection envelope. The envelope is...
INTEGRATED FILM, FILM, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND
METHOD FOR PRODUCING CHIP
Disclosed are an integrated film making it possible to detect, after the integrated film is bonded to a semiconductor wafer, a notch in this wafer; and others....
Electronic Component and Method for Electrically Coupling a Semiconductor
Die to a Contact Pad
In an embodiment, an electronic component includes a dielectric core layer, one or semiconductor dies comprising a first major surface, a first electrode...
3D TAP & SCAN PORT ARCHITECTURES
This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly...
INTEGRATED CIRCUIT COMPRISING AT LEAST AN INTEGRATED ANTENNA
An integrated circuit on a substrate includes a peripheral portion that surrounds an active area and is positioned close to a scribe line providing separation...
SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF
Forming a semiconductor arrangement includes non-destructively determining a first spacer height of a first sidewall spacer adjacent a dummy gate and a second...
Disclosed are apparatus and methods for characterizing a plurality of structures of interest on a semiconductor wafer. A plurality of models having varying...
METHOD OF SURFACE PROFILE CORRECTION USING GAS CLUSTER ION BEAM
A method for correcting a surface profile on a substrate is described. In particular, the method includes receiving a substrate having a heterogeneous layer...
METHOD AND APPARATUS FOR DETECTION OF FAILURES IN UNDER-FILL LAYERS IN
INTEGRATED CIRCUIT ASSEMBLIES
A methodology and circuitry enabling detection of smaller and early stages of failures in under-fill layers in IC chip assemblies are disclosed. Embodiments...
FIN FIELD EFFECT TRANSISTOR INCLUDING A STRAINED EPITAXIAL SEMICONDUCTOR
A semiconductor fin including a single crystalline semiconductor material is formed on a dielectric layer. A semiconductor shell including an epitaxial...
LOW-COST CMOS STRUCTURE WITH DUAL GATE DIELECTRICS AND METHOD OF FORMING
THE CMOS STRUCTURE
Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of...
INTEGRATION OF DEVICES
Devices and methods for forming a device are presented. A substrate with lightly doped first polarity type dopants is provided. A buried layer with heavily...
METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
A method for producing a semiconductor device includes forming a first fin-shaped semiconductor layer and a second fin-shaped semiconductor layer on a...
BLOCK LEVEL PATTERNING PROCESS
The present application relates to an optical planarizing layer etch process. Embodiments include forming fins separated by a dielectric layer; forming a...
GRAPHOEPITAXY DIRECTED SELF-ASSEMBLY PROCESS FOR SEMICONDUCTOR FIN
Guiding pattern portions are formed on a surface of a lithographic material stack that is disposed on a surface of a semiconductor substrate. A copolymer layer...