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VERTICAL CHANNEL-TYPE 3D SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR
MANUFACTURING THE SAME
A vertical channel-type 3D semiconductor memory device and a method for manufacturing the same are disclosed. In one aspect, the method includes depositing...
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a...
3D NAND DEVICE AND FABRICATION METHOD THEREOF
A method for forming a 3D NAND structure includes providing a semiconductor substrate; forming a control gate structure having a plurality of staircase-stacked...
3D VOLTAGE SWITCHING TRANSISTORS FOR 3D VERTICAL GATE MEMORY ARRAY
The area consumed by switching transistors for a 3D NAND memory array can be reduced with 3D voltage switching transistors with reduced aggregate area in...
THREE DIMENSIONAL MEMORY DEVICE WITH HYBRID SOURCE ELECTRODE FOR WAFER
The metallic material content of a contact via structure for a three-dimensional memory device can be reduced by employing a vertical stack of a doped...
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a charge storage pattern on a substrate, a blocking insulating pattern on the charge storage pattern, and a control gate...
THREE DIMENSIONAL MEMORY DEVICE HAVING WELL CONTACT PILLAR AND METHOD OF
A monolithic three dimensional memory device includes a semiconductor substrate having a major surface and a doped well region of a first conductivity type...
NONVOLATILE MEMORY DEVICE
A nonvolatile memory device may include a first well area formed on a substrate, a plurality of channel layers disposed on the first well area and extended in...
SEMICONDUCTOR MEMORY DEVICE
Provided is a semiconductor memory device including a floating gate formed of a semiconductor, which includes a first floating gate and a second floating gate...
A semiconductor device includes: a substrate having a plurality of active regions; a plurality of bit lines extending in a first direction, the plurality of...
SEMICONDUCTOR DEVICE INCLUDING AIR GAPS AND METHOD FOR FABRICATING THE
Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same....
SEMICONDUCTOR DEVICE OR ELECTRONIC COMPONENT INCLUDING THE SAME
A semiconductor device includes a memory cell, a buffer circuit, a switch, first to p-th switch circuits, and first to p-th capacitors (p is an integer of 2 or...
MEMORY STRUCTURE HAVING ARRAY-UNDER-PERIPHERY STRUCTURE
A memory structure is provided. The memory structure includes a substrate, an array portion disposed on the substrate, a periphery portion disposed on the...
SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF
A semiconductor arrangement and method of formation are provided. A semiconductor arrangement includes a first semiconductor device adjacent a second...
SEMICONDUCTOR DEVICE HAVING STRAIN-RELAXED BUFFER LAYER AND METHOD OF
MANUFACTURING THE SAME
A semiconductor device includes a substrate, a strain-relaxed buffer layer on the substrate, at least one well in the strain-relaxed buffer layer, a first...
DUAL MATERIAL FINFET ON SINGLE SUBSTRATE
A semiconductor device and a method for fabricating the device are provided. The semiconductor device has a substrate having a first device region and a second...
Mechanism for FinFET Well Doping
The embodiments of mechanisms for doping wells of finFET devices described in this disclosure utilize depositing doped films to dope well regions. The...
METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a...
FinFETs with Nitride Liners and Methods of Forming the Same
An integrated circuit structure includes a semiconductor substrate, which includes a semiconductor strip. A Shallow Trench Isolation (STI) region is on a side...
SEMICONDUCTOR DEVICE HAVING CONTACT PLUG AND METHOD OF FORMING THE SAME
A semiconductor device includes merged contact plugs. A multi-fin active having N sub-fins is formed in a substrate. A contact plug is formed on the impurity...
Semiconductor Device Having Strained Channel Layer and Method of
Manufacturing the Same
Semiconductor devices are provided. The semiconductor devices include active fins including a buffer layer disposed on a substrate and a channel layer disposed...
SUB-FIN DOPED BULK FIN FIELD EFFECT TRANSISTOR (FINFET), INTEGRATED
CIRCUIT (IC) AND METHOD OF MANUFACTURE
A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the IC. Fins on pedestals are defined, e.g., with a...
ROM Chip Manufacturing Structures
An integrated circuit (IC) chip embodiment includes first and second ROM cells arranged in a same row of a ROM array. The first and second ROM cells include...
Bidirectional Bipolar Power Devices with Two-Surface Optimization of
Striped Emitter/Collector Orientation
Two-surface bidirectional power bipolar transistors, in which the emitter/collector regions on the opposite surfaces of the die are each laid out as an array...
A small semiconductor device having a diode forward voltage less likely to change due to a gate potential is provided. An anode and an upper IGBT structure...
In the reverse-conducting IGBT according to the present invention, an n-type buffer layer surrounds a p-type collector layer. A p-type separation layer...
HIGH DENSITY CAPACITORS FORMED FROM THIN VERTICAL SEMICONDUCTOR STRUCTURES
SUCH AS FINFETS
A vertical structure may be manufactured in a substrate of an integrated circuit, and that vertical structure used to form a high density capacitance for the...
POWER SEMICONDUCTOR DEVICE AND METHOD THEREFOR
A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region...
FinFET-Based ESD Devices and Methods for Forming the Same
A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is...
DIODE, DIODE STRING CIRCUIT, AND ELECTROSTATIC DISCHARGE PROTECTION DEVICE
A diode includes a substrate, a first insulating layer, a second insulating layer, a well, a deep doped region, a first doped region, and a second doped...
IMMUNITY TO INLINE CHARGING DAMAGE IN CIRCUIT DESIGNS
Approaches for checking a design of an integrated circuit using an antenna rule are provided. A method includes determining a figure of merit for a transistor...
LIGHTING MODULE FOR EMITTING MIXED LIGHT
A lighting module for emitting mixed light comprises at least one first semiconductor element which emits unconverted red light, at least one second...
SEMICONDUCTOR DEVICE AND METHOD FOR DESIGNING IT
This semiconductor device (10) has a heat source element (HSE) and a thermosensor element (TE) on a semiconductor chip (SCH). The profile of the heat source...
SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
Provided are a semiconductor device and a fabricating method thereof. The fabricating method includes forming first to fourth fins, each extending in a first...
CELLS HAVING TRANSISTORS AND INTERCONNECTS INCLUDING NANOWIRES OR 2D
An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including...
SEMICONDUCTOR CHIP WITH OFFLOADED LOGIC
Various semiconductor chip and interposer devices are disclosed. In one aspect, an apparatus is provided that includes an interposer, a first semiconductor...
LIGHT EMITTING DEVICE PACKAGE
A light emitting device package is provided. The light emitting device package may include a main body having a cavity including side surfaces and a bottom,...
Methods of Forming Conductive and Insulating Layers
Methods of forming conductive and insulating layers for semiconductor devices and packages. Substrate is provided with integrated circuit device and...
An assembly can include a first microelectronic package and a circuit structure comprising a plurality of dielectric layers and electrically conductive...
WIRE BOND SUPPORT STRUCTURE AND MICROELECTRONIC PACKAGE INCLUDING WIRE
A microelectronic package may include a substrate having first and second regions, a first surface and a second surface remote from the first surface; at least...
Integrated Fan-Out Structure with Guiding Trenches in Buffer Layer
A bottom package includes a molding compound, a buffer layer over and contacting the molding compound, and a through-via penetrating through the molding...
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are...
STACKED PACKAGE DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating a stacked package device is provided. A second substrate is adhered onto a first substrate. The first substrate includes a plurality...
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
One device includes a first chip having first electrodes on one surface, and a rough portion on another surface. The device also includes a second chip having...
SEMICONDUCTOR DEVICE PACKAGES INCLUDING A CONTROLLER ELEMENT AND RELATED
Semiconductor device packages include a stack of semiconductor memory devices positioned over an interposer substrate, a controller element, and a...
Methods of Packaging Semiconductor Devices and Packaged Semiconductor
Packaged semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes a substrate and a plurality of integrated circuit...
METHOD FOR PREPARING LOW COST SUBSTRATES
A mask is formed over a first conductive portion of a conductive layer to expose a second conductive portion of the conductive layer. An electrolytic process...
NEW 2.5D MICROELECTRONIC ASSEMBLY AND METHOD WITH CIRCUIT STRUCTURE FORMED
A dielectric element has a plurality of contacts at a first surface and a plurality of first traces coupled thereto which extend in directions parallel to the...
FAN-OUT PACKAGE STRUCTURE INCLUDING ANTENNA
A semiconductor package structure including a first semiconductor package is provided. The first semiconductor package includes a first semiconductor package...
PACKAGE-ON-PACKAGE TYPE SEMICONDUCTOR DEVICE INCLUDING FAN-OUT MEMORY
A semiconductor device may include a bottom package embedded with a first semiconductor chip. The semiconductor device may include a middle package stacked...