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FIXTURE TO CONSTRAIN LAMINATE AND METHOD OF ASSEMBLY
A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip...
BOND HEADS FOR THERMOCOMPRESSION BONDERS, THERMOCOMPRESSION BONDERS, AND
METHODS OF OPERATING THE SAME
A bond head for a thermocompression bonder is provided. The bond head includes a tool configured to hold a workpiece to be bonded, a heater configured to heat...
SEMICONDUCTOR-MOUNTED PRODUCT AND METHOD OF PRODUCING THE SAME
A semiconductor-mounted product includes a semiconductor package, a circuit board, a solder bonding part, and a resin reinforcing part. Wiring is formed on the...
BALL BONDING METAL WIRE BOND WIRES TO METAL PADS
An apparatus, and methods therefor, relates generally to an integrated circuit package. In such an apparatus, a platform substrate has a copper pad. An...
Bonded Structures for Package and Substrate
The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially...
Semiconductor Package Configured for Connection to a Board
A semiconductor package includes a plurality of contact areas having a specific contact area and a plurality of solder balls applied to the contact areas. Two...
Packaging Devices, Methods of Manufacture Thereof, and Packaging Methods
Packaging devices, methods of manufacture thereof, and packaging methods are disclosed. In some embodiments, a packaging device includes a first substrate...
Reliable Device Assembly
Microelectronic assemblies and methods for making the same are disclosed herein. In one embodiment, a method of forming a microelectronic assembly comprises...
SILVER ALLOYING POST-CHIP JOIN
A method of forming a stacked surface arrangement for semiconductor devices includes joining a first surface to a second surface with a solder bump, the solder...
Semiconductor Structure With Sacrificial Anode and Method for Forming
A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over...
INDUCING DEVICE VARIATION FOR SECURITY APPLICATIONS
A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and regions, with implant regions and covered regions, in the...
POWER SEMICONDUCTOR DEVICE
A power semiconductor device is disclosed having a power semiconductor element with an upper and lower side, the upper side being located opposite to the lower...
SEMICONDUCTOR PACKAGES HAVING SEMICONDUCTOR CHIPS DISPOSED IN OPENING IN
SHIELDING CORE PLATE
A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first...
SEMICONDUCTOR PACKAGE WITH HIGH DENSITY DIE TO DIE CONNECTION AND METHOD
OF MAKING THE SAME
A semiconductor package according to some examples of the disclosure may include a substrate having a bridge embedded in the substrate, a first and second die...
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a first substrate, a second substrate, a dam layer, a photoresist layer, and a conductive layer. The first substrate has a...
EMBEDDED FUSE WITH CONDUCTOR BACKFILL
Embedded fuse structures and fabrication techniques. An embedded fuse may include a non-planar conductive line having two high-z portions extending to a...
Structure of integrated inductor
This invention discloses a structure of an integrated inductor, comprising: an outer metal segment which comprises a first metal sub-segment and a second metal...
Device-Manufacturing Scheme for Increasing the Density of Metal Patterns
in Inter-Layer Dielectrics
A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate...
Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect...
2D SELF-ALIGNED VIA FIRST PROCESS FLOW
A method of forming 2D self-aligned vias before forming a subsequent metal layer and reducing capacitance of the resulting device and the resulting device are...
SWITCHED-CAPACITOR DC-TO-DC CONVERTERS
A switched-capacitor DC-to-DC converter includes a first P-channel MOS transistor, a first N-channel MOS transistor, a second P-channel MOS transistor, and a...
SEMICONDUCTOR INTEGRATED CIRCUIT LAYOUT STRUCTURE
A semiconductor integrated circuit layout structure includes a first active region, a second active region isolating from the first active region, a gate...
PACKAGE SUBSTRATE AND METHODS FOR MANUFACTURING THE SAME
The present inventive concept provides a package substrate. The package substrate comprises an insulating substrate having a top surface a circuit pattern...
MULTILAYER SUBSTRATE FOR SEMICONDUCTOR PACKAGING
Embodiments disclosed include a multilayer substrate for semiconductor packaging. The substrate may include a first layer with a first side with an xy-plane...
THROUGH-HOLE ELECTRODE SUBSTRATE
A method of manufacturing a through-hole electrode substrate includes forming a plurality of through-holes in a substrate, forming a plurality of through-hole...
STACKED SEMICONDUCTOR DEVICE PACKAGE WITH IMPROVED INTERCONNECT BANDWIDTH
The present disclosure describes embodiments of a stacked semiconductor device package and associated techniques and configurations. A package may include a...
STACKING ARRANGEMENT FOR INTEGRATION OF MULTIPLE INTEGRATED CIRCUITS
A stacked integrated circuit (IC) system including a substrate, a contour support, and a first and second IC dies. The contour support including a first...
HIGH HEAT-DISSIPATION CHIP PACKAGE STRUCTURE
A high heat-dissipation chip package structure for packaging the semiconductor chips is disclosed. A pre-attachment film is adhered on an upper surface of a...
CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A chip package structure including a lead frame, a chip, a plurality of solder bumps, a solder resist layer and an encapsulant is provided. The lead frame has...
METHOD OF PROVIDING A FLEXIBLE SEMICONDUCTOR DEVICE AND FLEXIBLE
SEMICONDUCTOR DEVICE THEREOF
Some embodiments include a method. The method can include providing a carrier substrate, providing a release layer over the carrier substrate, and providing a...
ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF
An electronic package is provided, which includes: a circuit structure having opposite first and second sides; at least an electronic element disposed on the...
ELECTRONIC POWER DEVICE WITH IMPROVED COOLING
An electronic device comprising at least one electronic component mounted on a support and surrounded by a deformable casing containing a heat-conducting and...
PHASE CHANGING ON-CHIP THERMAL HEAT SINK
A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the...
A semiconductor assembly includes a stack with a semiconductor module and a cooler, wherein the semiconductor module is provided in contact with the cooler. A...
Semiconductor Device Having a Copper Element and Method of Forming a
Semiconductor Device Having a Copper Element
A semiconductor device includes a base element and a copper element over the base element. The copper element includes a layer stack having at least two copper...
SEMICONDUCTOR CHIP PACKAGE ASSEMBLY WITH IMPROVED HEAT DISSIPATION
A semiconductor chip package assembly includes a package substrate having a chip mounting surface; a plurality of solder pads disposed on the chip mounting...
Electronic device and fabrication method thereof
An electronic device is provided, which includes an electronic element and a heat dissipating element disposed on the electronic element through a thermal...
ELECTRONIC DEVICE INCLUDING A METAL SUBSTRATE AND A SEMICONDUCTOR MODULE
EMBEDDED IN A LAMINATE
An electronic device having a substrate including a metal layer, an electrically insulating layer disposed above the substrate, a semiconductor module disposed...
CIRCUIT CARRIER INCLUDING A SILICONE POLYMER COATING
A circuit carrier. The circuit carrier has at least one electronic component, the electronic component being soldered to the circuit carrier, in particular...
METHOD AND APPARATUS FOR BOND-PAD CHARGING PROTECTION OF TRANSISTOR TEST
A method for preparing a non-reference transistor test structure having multiple terminals is disclosed. The method may include when an intended application of...
SEMICONDUCTOR DEVICE AND METHOD OF ADAPTIVE PATTERNING FOR PANELIZED
PACKAGING WITH DYNAMIC VIA CLIPPING
A semiconductor device and method of adaptive patterning for panelized packaging with dynamic via clipping is described. A panel comprising an encapsulating...
METHODS AND APPARATUS FOR CONTROLLING SUBSTRATE UNIFORMITY
A dynamically tunable process kit, a processing chamber having a dynamically tunable process kit, and a method for processing a substrate using a dynamically...
SEMICONDUCTOR DEVICE, MEASUREMENT APPARATUS, AND MEASUREMENT METHOD OF
The field of an oxide semiconductor has been attracted attention in recent years. Therefore, the correlation between electric characteristics of a transistor...
SELECTIVE THICKENING OF PFET DIELECTRIC
A complementary metal-oxide semiconductor (CMOS) device and a method of fabricating a CMOS device are described. The method includes forming an interfacial...
INTEGRATED TENSILE STRAINED SILICON NFET AND COMPRESSIVE STRAINED
SILICON-GERMANIUM PFET IMPLEMENTED IN FINFET...
A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area....
Multi-Gate Device Structure Including a Fin-Embedded Isolation Region and
A structure and method for implementation of high voltage devices within multi-gate device structures includes a substrate having a fin extending therefrom and...
UNIDIRECTIONAL SPACER IN TRENCH SILICIDE
A semiconductor device includes a trench region in an interconnect level dielectric layer. A silicide layer is on the bottom of the trench region. Opposing...
SEMICONDUCTOR DEVICE AND FORMATION THEREOF
A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a doped region, in some embodiments. The...
ISOLATION COMPONENTS FOR TRANSISTORS FORMED ON FIN FEATURES OF
In an embodiment, a method comprises: forming a fin feature on a portion of a surface of a substrate; forming a first region of polycrystalline silicon over a...
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating...