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Patent # Description
2016/0336454 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A miniaturized transistor with less variation and highly stable electrical characteristics is provided. Further, high performance and high reliability of a...
2016/0336453 ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE
An array substrate provided according to the present disclosure may include: a base substrate; a gate electrode and a gate insulating layer sequentially formed...
2016/0336452 Thin Film Transistor and Method of Fabricating the Same, Array Substrate, and Display Device
The present invention provides a thin film transistor and a method of fabricating the same, an array substrate and a display device. The thin film transistor...
2016/0336451 NON-PLANAR TRANSISTOR AND METHOD OF FORMING THE SAME
A non-planar transistor is provided. It includes a substrate, a fin structure, a gate structure, a spacer structure and a source/drain region. The fin...
2016/0336450 SEMICONDUCTOR DEVICE INCLUDING FIELD EFFECT TRANSISTORS
A semiconductor device includes a fin structure on a substrate and extending in a first direction, a gate electrode crossing over the fin structure,...
2016/0336449 SEMICONDUCTOR TRANSISTOR HAVING BUFFER LAYER BETWEEN CHANNEL AND SUBSTRATE
FinFET and fabrication method thereof. The FinFET fabrication method includes providing a semiconductor substrate; forming a plurality of trenches in the...
2016/0336448 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
A method of fabricating a semiconductor device. The method includes forming an isolation feature in a substrate, forming a first gate stack and a second gate...
2016/0336447 METHOD FOR IMPROVING TRANSISTOR PERFORMANCE THROUGH REDUCING THE SALICIDE INTERFACE RESISTANCE
An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a...
2016/0336446 METHOD FOR IMPROVING TRANSISTOR PERFORMANCE THROUGH REDUCING THE SALICIDE INTERFACE RESISTANCE
An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a...
2016/0336445 Tuning Strain in Semiconductor Devices
A Fin Field-Effect Transistor (FinFET) includes a semiconductor layer over a substrate, wherein the semiconductor layer forms a channel of the FinFET. A first...
2016/0336444 SEMICONDUCTOR DEVICE
A semiconductor device includes a fin-shaped silicon layer on a silicon substrate surface. The fin-shaped silicon layer has a longitudinal axis extending in a...
2016/0336443 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
In a vertical MOSFET in which bottom portions of each gate electrode formed in a ditch are extended toward the drain region, the on resistance is reduced while...
2016/0336442 INTEGRATED HIGH SIDE GATE DRIVER STRUCTURE AND CIRCUIT FOR DRIVING HIGH SIDE POWER TRANSISTORS
The present invention relates to an integrated high side gate driver structure for driving a power transistor. The high side gate driver structure comprises a...
2016/0336441 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor layer made of SiC. A transistor element having an impurity region is formed in a front surface portion of the...
2016/0336440 SUPER JUNCTION DEVICE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing super junction device includes forming a first epitaxial layer on a semiconductor substrate. The first epitaxial layer is patterned...
2016/0336439 NONVOLATILE MEMORY DEVICE USING TWO-DIMENSIONAL MATERIAL AND METHOD OF MANUFACTURING THE SAME
Example embodiments relate to nonvolatile memory devices using a 2D material, and methods of manufacturing the nonvolatile memory device. The nonvolatile...
2016/0336438 COMPOUND SEMICONDUCTOR DEVICE
A compound semiconductor device includes: a substrate; and a buffer layer, a first carrier supply layer, a first spacer layer, a channel layer, a second spacer...
2016/0336437 FIELD EFFECT TRANSISTOR
A field effect transistor having a reduced sheet resistance is provided. A channel layer, a first spacer layer, a second spacer layer, a first electronic...
2016/0336436 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
In one aspect of the present disclosure, a semiconductor device includes a channel layer, an Al.sub.xIn.sub.1-xN layer on the channel layer with a thickness of...
2016/0336435 SEMICONDUCTOR DEVICE
When formed to have a lattice pattern, trenches are deeper at the portions thereof corresponding to the vertices of the lattice pattern than at the portions...
2016/0336434 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor layer may be subjected to etching to form a trench therein. An epitaxial layer may be further formed in the trench. Here, the impurity...
2016/0336433 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
To improve the electrical characteristics of a semiconductor device including an oxide semiconductor, and to provide a highly reliable semiconductor device...
2016/0336432 TRENCH VERTICAL JFET WITH IMPROVED THRESHOLD VOLTAGE CONTROL
Trench JFETs may be created by etching trenches into the topside of a substrate of a first doping type to form mesas. The substrate is made up of a backside...
2016/0336431 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device, which includes the steps of forming a gate stack structure made up of a floating gate, an inter-poly...
2016/0336430 METHOD OF MANUFACTURING A HORIZONTAL GATE-ALL-AROUND TRANSISTOR HAVING A FIN
A semiconductor structure includes a substrate and a fin. The fin extends from the substrate and is formed with a hole therethrough. The hole is defined by a...
2016/0336429 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure,...
2016/0336428 LOCAL SOI FINS WITH MULTIPLE HEIGHTS
A semiconductor structure is provided that contains silicon fins having different heights, while maintaining a reasonable fin height to width ratio for process...
2016/0336427 DILUTED DRIFT LAYER WITH VARIABLE STRIPE WIDTHS FOR POWER TRANSISTORS
A multi-finger lateral high voltage transistors (MFLHVT) includes a substrate doped a first dopant type, a well doped a second dopant type, and a buried drift...
2016/0336426 SEMICONDUCTOR STRUCTURE WITH UNLEVELED GATE STRUCTURE AND METHOD FOR FORMING THE SAME
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a...
2016/0336425 MULTICHANNEL DEVICES WITH IMPROVED PERFORMANCE AND METHODS OF MAKING THE SAME
A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge...
2016/0336424 SELF-ALIGNED SOURCE AND DRAIN REGIONS FOR SEMICONDUCTOR DEVICES
A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate...
2016/0336423 METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE
A semiconductor structure is formed in a SiC substrate. A thermal oxide film is formed on a front surface of the SiC substrate. An opening reaching the front...
2016/0336422 HIGH-K METAL GATE
An integrated circuit containing metal replacement gates may be formed by forming a nitrogen-rich titanium-based barrier between a high-k gate dielectric layer...
2016/0336421 DUAL WORK FUNCTION INTEGRATION FOR STACKED FINFET
A three-dimensional stacked fin complementary metal oxide semiconductor (CMOS) device having dual work function metal gate structures is provided. The stacked...
2016/0336420 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A method of manufacturing a Fin FET includes forming a fin structure including an upper layer. Part of the upper layer is exposed from an isolation insulating...
2016/0336419 THIN FILM TRANSISTOR AND BACKPLANE SUBSTRATE OF A DISPLAY DEVICE INCLUDING THE SAME
A thin film transistor includes a gate electrode on a substrate. The gate electrode includes a flat portion and an inclined portion at a side of the flat...
2016/0336418 SELF-ALIGNED SOURCE AND DRAIN REGIONS FOR SEMICONDUCTOR DEVICES
A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate...
2016/0336417 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; using a first patterned mask to form a...
2016/0336416 Semiconductor Device Structure and Method
A multi-layered semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor layer, a first insulator layer, a second...
2016/0336415 MEMORY CELL STRUCTURE FOR IMPROVING ERASE SPEED
A split-gate flash memory cell for improved erase speed is provided. An erase gate and a floating gate are laterally spaced over a semiconductor substrate. The...
2016/0336414 DUAL WORK FUNCTION BURIED GATE-TYPE TRANSISTOR, METHOD FOR FORMING THE SAME, AND ELECTRONIC DEVICE INCLUDING...
A transistor includes: a source region and a drain region that are formed in a substrate to be spaced apart from each other; a trench formed in the substrate...
2016/0336413 RECESS ARRAY DEVICE WITH REDUCED CONTACT RESISTANCE
A recess array device includes a semiconductor substrate having a main surface; a recessed trench in the main surface of the semiconductor substrate; a gate...
2016/0336412 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a semiconductor substrate, at least one dielectric layer, a dielectric spacer liner (DSL) layer, and at least one conductor....
2016/0336411 RECESSED CONTACT TO SEMICONDUCTOR NANOWIRES
A semiconductor nanowire device includes at least one semiconductor nanowire having a bottom surface and a top surface, an insulating material which surrounds...
2016/0336410 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a source region, a drain region, a...
2016/0336409 Semiconductor Device Having an Impurity Concentration and Method of Manufacturing Thereof
A method of manufacturing a semiconductor device includes irradiating the semiconductor body with particles through a first side of the semiconductor body,...
2016/0336408 REDUCTION OF DEFECT INDUCED LEAKAGE IN III-V SEMICONDUCTOR DEVICES
A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 10.sup.8...
2016/0336407 SEMICONDUCTOR DEVICES WITH SUPERLATTICE LAYERS PROVIDING HALO IMPLANT PEAK CONFINEMENT AND RELATED METHODS
A semiconductor device may include a semiconductor substrate, and a plurality of field effect transistors (FETs) on the semiconductor substrate. Each FET may...
2016/0336406 SEMICONDUCTOR DEVICES WITH SUPERLATTICE AND PUNCH-THROUGH STOP (PTS) LAYERS AT DIFFERENT DEPTHS AND RELATED METHODS
A semiconductor device may include a semiconductor substrate and first transistors having a first operating voltage. Each first transistor may include a first...
2016/0336405 HORIZONTAL GATE ALL AROUND AND FINFET DEVICE ISOLATION
Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor...
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