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Patent # Description
2016/0336254 SUBSTRATE WITH EMBEDDED SINTERED HEAT SPREADER AND PROCESS FOR MAKING THE SAME
The present disclosure relates to a substrate with an embedded sintered heat spreader and a process for making the same. According to an exemplary process, at...
2016/0336253 HEAT DISSIPATION SUBSTRATE AND METHOD FOR PRODUCING HEAT DISSIPATION SUBSTRATE
A heat dissipation substrate having a metallic layer with few defects on its surface is obtained by a process including the steps of: forming a metallic layer...
2016/0336252 Semiconductor Module
An object of the present invention is to provide a semiconductor module that can improve the dissipation of heat from semiconductor elements toward a cooling...
2016/0336251 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor chip, a metal member, and a terminal. The semiconductor chip has an electrode. The metal member is electrically...
2016/0336250 SEMICONDUCTOR DEVICE
A semiconductor device includes: a semiconductor substrate having a main plane; a semiconductor element provided on the main plane of the semiconductor...
2016/0336249 ELECTRONIC COMPONENT PACKAGE AND METHOD OF MANUFACTURING THE SAME
An electronic component package includes a frame having a cavity, an electronic component disposed in the cavity of the frame, a first metal layer disposed on...
2016/0336248 CURED PRODUCT
The present application relates to a cured product and the use thereof. When the cured product, for example, is applied to a semiconductor device such as an...
2016/0336247 Molding Structure for Wafer Level Package
Apparatus, and methods of manufacture thereof, in which a molding compound is formed between spaced apart microelectronic devices. The molding compound...
2016/0336246 SEMICONDUCTOR ENCAPSULATION RESIN COMPOSITION AND SEMICONDUCTOR DEVICE COMPRISED OF CURED PRODUCT OF THE...
Provided is a semiconductor encapsulation resin composition exhibiting an insignificant heat decomposition when left under a high temperature of 200 to...
2016/0336245 POWER SEMICONDUCTOR DEVICE
A power semiconductor device includes: an outer case; at least one press-fit terminal buried in a top surface of the outer case; and a plurality of supporting...
2016/0336244 SEMICONDUCTOR DEVICE
Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening...
2016/0336243 METHOD FOR TESTING SEMICONDUCTOR WAFERS USING TEMPORARY SACRIFICIAL BOND PADS
A method is provided for testing a semiconductor wafer, including individual semiconductor devices located on the semiconductor wafer, using temporary...
2016/0336242 METHOD FOR WAFER LEVEL RELIABILITY
A method for ensuring wafer level reliability is provided. The method involves: forming a gate oxide layer having a thickness of less than 50 .ANG. on a...
2016/0336241 AUTOMATED OPTICAL INSPECTION OF UNIT SPECIFIC PATTERNING
A method of automated optical inspection (AOI) for a plurality of unique semiconductor packages can comprise providing a plurality of semiconductor die formed...
2016/0336240 ALIGNMENT MONITORING STRUCTURE AND ALIGNMENT MONITORING METHOD FOR SEMICONDUCTOR DEVICES
The present disclosure provides in various aspects an alignment monitoring structure and method for monitoring the alignment between a target gate conductor...
2016/0336239 POLYSILICON RESISTOR FORMATION IN SILICON-ON-INSULATOR REPLACEMENT METAL GATE FINFET PROCESSES
A method of forming a polysilicon resistor in replacement metal gate (RMG) processing of finFET devices includes forming a plurality of semiconductor fins over...
2016/0336238 POLYSILICON RESISTOR FORMATION IN SILICON-ON-INSULATOR REPLACEMENT METAL GATE FINFET PROCESSES
A method of forming a polysilicon resistor in replacement metal gate (RMG) processing of finFET devices includes forming a plurality of semiconductor fins over...
2016/0336237 Strain Enhancement for FinFETs
An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first...
2016/0336236 DUAL FIN INTEGRATION FOR ELECTRON AND HOLE MOBILITY ENHANCEMENT
A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer. Spacers are formed...
2016/0336235 DUAL WORK FUNCTION INTEGRATION FOR STACKED FINFET
A three-dimensional stacked fin complementary metal oxide semiconductor (CMOS) device having dual work function metal gate structures is provided. The stacked...
2016/0336234 SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME
Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating...
2016/0336233 SYSTEMS AND METHODS FOR LASER SPLITTING AND DEVICE LAYER TRANSFER
Methods and systems are provided for the split and separation of a layer of desired thickness of crystalline semiconductor material containing optical,...
2016/0336232 CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A chip package structure and the manufacturing method thereof are provided. Firstly, a conductive frame including a bottom plate and a plurality of partition...
2016/0336231 INTERCONNECT STRUCTURE FOR CONNECTING DIES AND METHODS OF FORMING THE SAME
A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first...
2016/0336230 Semiconductor Device and Method of Forming a Thin Wafer Without a Carrier
A semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the...
2016/0336229 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
Various embodiments provide semiconductor structures and methods for forming the same. In an exemplary structure, a substrate has a device region, a seal ring...
2016/0336228 BACKSIDE CAVITY FORMATION IN SEMICONDUCTOR DEVICES
Fabrication of radio-frequency (RF) devices involves providing a field-effect transistor (FET) formed over an oxide layer formed on a semiconductor substrate,...
2016/0336227 METHOD OF FORMING CONTACT STRUCUTRE
A method of forming a contact structure is provided. A silicon-containing substrate is provided with a composite dielectric layer formed thereon. An opening...
2016/0336226 Method of reducing a sheet resistance in an electronic device, and an electronic device
Various embodiments provide a method of reducing a sheet resistance in an electronic device encapsulated at least partially in an encapsulation material,...
2016/0336225 VIA FORMATION USING SIDEWALL IMAGE TRANSFER PROCESS TO DEFINE LATERAL DIMENSION
A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using...
2016/0336224 METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND SILICON CARBIDE SEMICONDUCTOR DEVICE
A method of manufacturing a silicon carbide semiconductor device includes forming on a front surface of a silicon carbide substrate of a first conductivity...
2016/0336223 SUBSTRATE CONDUCTOR STRUCTURE AND METHOD
Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and...
2016/0336222 Tungsten Films by Organometallic or Silane Pre-Treatment of Substrate
Processing methods comprising exposing a substrate to a nucleation promoter followed by sequential exposure of a first reactive gas comprising a...
2016/0336221 Via Corner Engineering in Trench-First Dual Damascene Process
An integrated circuit structure includes a first dielectric layer, an etch stop layer over the first dielectric layer, and a second dielectric layer over the...
2016/0336220 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
A semiconductor device includes a substrate including a memory cell region and a contact region, a string structure including conductive layers and first...
2016/0336219 ISOLATED AND BULK SEMICONDUCTOR DEVICES FORMED ON A SAME BULK SUBSTRATE
Isolated and bulk semiconductor devices formed on a same bulk substrate and methods to form such devices are described. For example, a semiconductor structure...
2016/0336218 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
A method for manufacturing a semiconductor device includes etching a semiconductor substrate to form a fin-shaped semiconductor layer. After forming the...
2016/0336217 Method for Filling the Trenches of Shallow Trench Isolation (STI) Regions
A method for manufacturing a shallow trench isolation (STI) region with a high aspect ratio is provided. A semiconductor substrate is provided with a trench. A...
2016/0336216 AIR-GAP SCHEME FOR BEOL PROCESS
The present disclosure relates a back-end-of-the-line (BEOL) metallization stack having an air gap disposed between adjacent metal interconnect features, which...
2016/0336215 CALIBRATION METHOD FOR HEAT TREATMENT UNITS
A calibration method for determining temperature set point corrections to be applied to the nominal temperature set points of each of the N heating zones of a...
2016/0336214 CAVITY FORMATION IN INTERFACE LAYER IN SEMICONDUCTOR DEVICES
Fabrication of radio-frequency (RF) devices involves providing a field-effect transistor (FET), forming one or more electrical connections to the FET, forming...
2016/0336213 HIGH TEMPERATURE SUBSTRATE PEDESTAL MODULE AND COMPONENTS THEREOF
A semiconductor substrate processing apparatus comprises a vacuum chamber in which a semiconductor substrate may be processed, a showerhead module through...
2016/0336212 APPARATUS, SYSTEM, AND METHOD FOR HANDLING ALIGNED WAFER PAIRS
An industrial-scale apparatus, system, and method for handling precisely aligned and centered semiconductor wafer pairs for wafer-to-wafer aligning and bonding...
2016/0336211 BONDING STRUCTURE, METHOD OF MANUFACTURING THE SAME, AND DIE STRUCTURE
A bonding structure including a first substrate, a second substrate, and an adhesive layer is provided. The first substrate has a plurality of first trenches....
2016/0336210 Electrostatic Chuck and Method of Making Same
An electrostatic chuck includes a ceramic structural element, at least one electrode disposed on the ceramic structural element, and a surface dielectric layer...
2016/0336209 Container Transport Device and Container Transport Facility
A support member includes a first positioning portion for properly positioning a small container, and a second positioning portion for properly positioning a...
2016/0336208 APPARATUS, SYSTEM, AND METHOD FOR HANDLING ALIGNED WAFER PAIRS
An industrial-scale apparatus, system, and method for handling precisely aligned and centered semiconductor wafer pairs for wafer-to-wafer aligning and bonding...
2016/0336207 METHOD AND SYSTEM FOR TRANSFERRING SEMICONDUCTOR DEVICES FROM A WAFER TO A CARRIER STRUCTURE
Embodiments of methods and system for transferring semiconductor devices from a wafer to a carrier structure are described. In one embodiment, a method for...
2016/0336206 SYSTEM AND METHOD FOR MONITORING WAFER HANDLING AND A WAFER HANDLING MACHINE
Systems, machines, and methods for monitoring wafer handling are disclosed herein. A system for monitoring wafer handling includes a sensor and a controller....
2016/0336205 ABSORBING LAMPHEAD FACE
The embodiments described herein generally relate to a lamphead assembly with an absorbing upper surface in a thermal processing chamber. In one embodiment, a...
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