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| Patent # | Description |
|---|---|
| 2016/0343633 |
THIN FILM BASED FAN OUT AND MULTI DIE PACKAGE PLATFORM Thin film based fan out wafer level packaging and a method of manufacturing the same are disclosed. Embodiments include a method including forming tapered via... |
| 2016/0343632 |
CHIP PACKAGE HAVING A PATTERNED CONDUCTING PLATE AND METHOD FOR FORMING
THE SAME A chip package includes a patterned conducting plate having a plurality of conducting sections electrically separated from each other, a plurality of... |
| 2016/0343631 |
SEMICONDUCTOR DEVICES COMPRISING GETTER LAYERS AND METHODS OF MAKING AND
USING THE SAME Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or... |
| 2016/0343630 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME A semiconductor device includes a metal member, a semiconductor element, a resin part, a primer layer, and a peel-off restraining part. The metal member has a... |
| 2016/0343629 |
WAFER STACK PROTECTION SEAL A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing a wafer stack with first and second... |
| 2016/0343628 |
ELEMENT-ACCOMMODATING PACKAGE AND MOUNTING STRUCTURE An element-accommodating package which can improve frequency characteristics of an element-accommodating package having a coaxial connector, and a mounting... |
| 2016/0343627 |
SEMICONDUCTOR DEVICE A purpose of the present invention is to provide a semiconductor device that can restrain occurrence of partial discharge in evaluation of electric... |
| 2016/0343626 |
THERMOCOMPRESSION BONDERS, METHODS OF OPERATING THERMOCOMPRESSION BONDERS,
AND HORIZONTAL CORRECTION MOTIONS... A method of operating a thermocompression bonding system is provided. The method includes the steps of: (a) applying a first level of bond force to a... |
| 2016/0343625 |
METHOD AND SYSTEM FOR CONTROLLING PLASMA IN SEMICONDUCTOR FABRICATION A plasma processing system and a method for controlling a plasma in semiconductor fabrication are provided. The system includes a remote plasma module... |
| 2016/0343624 |
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE A method of manufacturing a semiconductor device includes: forming lower-layer wirings for a transistor, a circuit element and a plurality of contact pads on a... |
| 2016/0343623 |
IMPLANT-FREE PUNCH THROUGH DOPING LAYER FORMATION FOR BULK FINFET
STRUCTURES A punch through stop layer is formed in a bulk FinFET structure using doped oxides. Dopants are driven into the substrate and base portions of the fins by... |
| 2016/0343622 |
SELECTIVE THICKENING OF PFET DIELECTRIC A complementary metal-oxide semiconductor (CMOS) device and a method of fabricating a CMOS device are described. The method includes forming an interfacial... |
| 2016/0343621 |
DIRECTLY FORMING SiGe FINS ON OXIDE Semiconductor mandrel structures are formed extending upward from a remaining portion of a semiconductor substrate. A first oxide isolation structure is formed... |
| 2016/0343620 |
Nano Wire Structure and Method for Fabricating the Same A method comprises applying a first patterning process to a first photoresist layer to form a first opening, a second opening, a third opening and a fourth... |
| 2016/0343619 |
SUBSTRATE DIVIDING METHOD A substrate dividing method which can thin and divide a substrate while preventing chipping, and cracking from occurring. This substrate dividing method... |
| 2016/0343618 |
SUBSTRATE DIVIDING METHOD A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method... |
| 2016/0343617 |
SUBSTRATE DIVIDING METHOD A substrate dividing method which can thin and divide a substrate while preventing chipping, and cracking from occurring. This substrate dividing method... |
| 2016/0343616 |
SEMICONDUCTOR DEVICE INCLUDING AT LEAST ONE ELEMENT A semiconductor device includes a chip, at least one element electrically coupled to the chip, an adhesive at least partially covering the at least one... |
| 2016/0343615 |
Methods of Packaging Semiconductor Devices and Structures Thereof Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes... |
| 2016/0343614 |
WAFER PROCESSING METHOD A wafer having a substrate and a functional layer formed on the front side of the substrate is processed by attaching a protective tape curable by an external... |
| 2016/0343613 |
THROUGH-DIELECTRIC-VIAS (TDVs) FOR 3D INTEGRATED CIRCUITS IN SILICON Through-dielectric-vias (TDVs) for 3D integrated circuits in silicon are provided. Example structures and processes fabricate conductive vertical pillars for... |
| 2016/0343612 |
FEATURE FILL WITH MULTI-STAGE NUCLEATION INHIBITION Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some... |
| 2016/0343611 |
INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a... |
| 2016/0343610 |
STITCHED DEVICES A stitched device is disclosed. The stitched device includes first and second base devices having first and second stitched interconnects electrically coupled... |
| 2016/0343609 |
TECHNIQUES FOR TRENCH ISOLATION USING FLOWABLE DIELECTRIC MATERIALS Techniques are disclosed for providing trench isolation of semiconductive fins using flowable dielectric materials. In accordance with some embodiments, a... |
| 2016/0343608 |
SHALLOW TRENCH ISOLATION TRENCHES AND METHODS FOR NAND MEMORY A method of forming a shallow trench isolation trench in a semiconductor substrate is described. The method includes forming a trench in a region of the... |
| 2016/0343607 |
PRESERVING THE SEED LAYER ON STI EDGE AND IMPROVING THE EPITAXIAL GROWTH A method of forming self-aligned STI regions extending over portions of a Si substrate to enable the subsequent formation of epitaxially grown embedded S/D... |
| 2016/0343606 |
AIR GAP FORMING TECHNIQUES BASED ON ANODIC ALUMINA FOR INTERCONNECT
STRUCTURES An aluminum (Al) layer is formed over a semiconductor substrate. A selective portion of the Al layer is removed to form openings. The Al layer is anodized to... |
| 2016/0343605 |
Solvent-Based Oxidation on Germanium and III-V Compound Semiconductor
Materials A method to provide an isolation feature over a semiconductor structure is disclosed. The method includes forming a fin structure over a semiconductor... |
| 2016/0343604 |
SUBSTRATE STRUCTURE WITH EMBEDDED LAYER FOR POST-PROCESSING SILICON HANDLE
ELIMINATION The present disclosure relates to a substrate structure with a buried dielectric layer for post-processing silicon handle elimination. The substrate structure... |
| 2016/0343603 |
WAFER TRANSPORT DEVICE A wafer transport device including a robot arm and a C-ring is provided. The C-ring is disposed on the robot aim. The C-ring includes a C-ring body and a... |
| 2016/0343602 |
WORKPIECE CLAMP A workpiece clamp including an inner ring is provided. The inner edge of the inner ring can be divided into a circular arc portion and two first line portions.... |
| 2016/0343601 |
METHOD OF PREPARING LAMINATE, AND METHOD OF SEPARATING SUPPORT A method of preparing a laminate, in which the laminate has a substrate and a support plate, and is provided with a release layer capable of being altered by... |
| 2016/0343600 |
ELECTROSTATIC PUCK ASSEMBLY WITH METAL BONDED BACKING PLATE FOR HIGH
TEMPERATURE PROCESSES An electrostatic puck assembly includes an upper puck plate, a lower puck plate and a backing plate. The upper puck plate comprises AlN or Al.sub.2O.sub.3 and... |
| 2016/0343599 |
PROCESSING APPARATUS A temporary receiving unit of a processing apparatus includes a first support rail having a first bottom wall and a first side wall for guiding a workpiece for... |
| 2016/0343598 |
SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND FOUP TO BE USED THEREFOR A semiconductor device manufacturing method which uses a FOUP capable of suppressing semiconductor substrate defects due to outgas. The FOUP includes: a main... |
| 2016/0343597 |
APPARATUS FOR TREATING SUBSTRATE A substrate-treating apparatus according to an example embodiment of the inventive concepts includes a support unit on which a substrate is loaded, an optical... |
| 2016/0343596 |
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE Provided is a semiconductor device that suppresses the occurrence of defects due to photocorrosion. A method for manufacturing the semiconductor device... |
| 2016/0343595 |
CORROSION RESISTANT GAS DISTRIBUTION MANIFOLD WITH THERMALLY CONTROLLED
FACEPLATE An apparatus for semiconductor manufacturing is provided. The apparatus may include a gas distribution manifold. The gas distribution manifold may include a... |
| 2016/0343594 |
WET ETCHING MACHINE AND ETCHING METHOD USING THE SAME The present disclosure provides a wet etching machine and an etching method. The wet etching machine including an etching chamber in which at least two etching... |
| 2016/0343593 |
SEMICONDUCTOR PACKAGE INCLUDING PREMOLD AND METHOD OF MANUFACTURING THE
SAME A semiconductor package including a premold which is used to define support structure for a semiconductor die which is mounted to the premold by a layer of... |
| 2016/0343592 |
FLIP CHIP MODULE WITH ENHANCED PROPERTIES A flip chip module having at least one flip chip die is disclosed. The flip chip module includes a carrier having a top surface with a first mold compound... |
| 2016/0343591 |
REDUCTION OF UNDERFILL FILLER SETTLING IN INTEGRATED CIRCUIT PACKAGES Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with... |
| 2016/0343590 |
POWER MODULE AND FABRICATION METHOD FOR THE SAME The power module includes: a first metallic circuit pattern, a semiconductor device disposed on the first metallic circuit pattern; a leadframe electrically... |
| 2016/0343589 |
DEPOSITION APPARATUS, APPARATUS FOR SUCCESSIVE DEPOSITION, AND METHOD FOR
MANUFACTURING SEMICONDUCTOR DEVICE An oxide semiconductor layer is formed with a deposition apparatus including a transfer mechanism for a substrate, a first deposition chamber in which an oxide... |
| 2016/0343588 |
USE OF GRAPHO-EPITAXIAL DIRECTED SELF-ASSEMBLY APPLICATIONS TO PRECISELY
CUT LOGIC LINES A method for patterning topography is provided. A substrate is provided with a plurality of lines. The method includes aligning and preparing a first directed... |
| 2016/0343587 |
WIRING BOARD, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHODS THEREOF It is an object to reduce defective conduction in a wiring board or a semiconductor device whose integration degree is increased. It is another object to... |
| 2016/0343586 |
METHOD FOR PATTERNING OF LAMINATED MAGNETIC LAYER A microelectronic device is formed by forming a stack of alternating layers of a magnetic material and a dielectric material. An etch mask is formed over the... |
| 2016/0343585 |
CONTACT STRUCTURE AND EXTENSION FORMATION FOR III-V NFET FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the... |
| 2016/0343584 |
HEAT TREATMENT APPARATUS EMITTING FLASH OF LIGHT Flash lamps connected to short-pulse circuits and flash lamps connected to long-pulse circuits are alternately arranged in a line. The duration of light... |
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