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Patent # Description
2016/0351499 SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE
A semiconductor device includes a semiconductor substrate, a through hole via which pierces the semiconductor substrate, and a wiring layer (multilayer...
2016/0351498 ANTIFUSE ELEMENT USING SPACER BREAKDOWN
Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, including both non-volatile and volatile...
2016/0351497 COBALT-CONTAINING CONDUCTIVE LAYERS FOR CONTROL GATE ELECTRODES IN A MEMORY STRUCTURE
A memory stack structure including a memory film and a vertical semiconductor channel can be formed within each memory opening that extends through a stack...
2016/0351496 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
A method for fabricating a semiconductor structure includes providing a dielectric layer on a semiconductor substrate, forming an opening in the dielectric...
2016/0351495 PROCESS FOR MANUFACTURING INTEGRATED ELECTRONIC DEVICES, IN PARTICULAR CMOS DEVICES USING A BORDERLESS CONTACT...
For manufacturing an integrated electronic device, a protection layer, of a first material, is formed over a body having a non-planar surface; a first...
2016/0351494 DEVICE, PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME
Device, package structure and method of forming the same are disclosed. The device includes a die encapsulated by an encapsulant, a conductive structure aside...
2016/0351493 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME
A semiconductor device is provided, which includes a first conductive layer disposed on a substrate, a dielectric layer with at least an opening disposed on...
2016/0351492 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A through electrode and a multilayer wiring are provided on a semiconductor substrate, and a bottom layer connection wiring, a lower layer connection wiring,...
2016/0351491 WIRING STRUCTURE AND ELECTRONIC DEVICE INCLUDING THE SAME
A wiring structure may include at least two conductive material layers and a two-dimensional layered material layer in an interface between the at least two...
2016/0351490 CROSS-COUPLE IN MULTI-HEIGHT SEQUENTIAL CELLS FOR UNI-DIRECTIONAL M1
A MOS device includes first, second, third, and fourth interconnects. The first interconnect extends on a first track in a first direction. The first...
2016/0351489 SUB-TERAHERTZ/TERAHERTZ INTERCONNECT
An interconnect is described that comprises an interconnect channel, and two channel couplers coupled to the two ends of the interconnect channel through...
2016/0351488 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
The semiconductor device 1 includes an insulating substrate 2, a conductive part 3 that extends in a first direction, a conductive part 4 that is separated in...
2016/0351487 SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR
Provided is a semiconductor device having a wiring structure on a semiconductor element and capable of securing high quality and high reliability in response...
2016/0351486 Semiconductor Device and Method of Forming Substrate Including Embedded Component with Symmetrical Structure
A semiconductor device comprises a first conductive layer. A second conductive layer is formed over the first conductive layer. A semiconductor component is...
2016/0351485 SUBSTRATE DEVICE AND ELECTRIC CIRCUIT ARRANGEMENT
An electronic circuit includes a substrate device which includes a first substrate section including a first plurality of layers attached to each other having...
2016/0351484 HIGH EFFICIENCY MODULE
A module (1) includes a first functional device (2) and a second functional device (3). The first functional device (2) includes a base electrode, an emitter...
2016/0351483 CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING CHIP PACKAGE
The present disclosure relates to a chip package structure and a method for forming a chip package. A package unit is formed from the chip and an encapsulant...
2016/0351482 ETCHING-BEFORE-PACKAGING THREE-DIMENSIONAL SYSTEM-LEVEL METAL CIRCUIT BOARD STRUCTURE INVERSELY PROVIDED WITH...
Provided is an etching-before-packaging three-dimensional system-level metal circuit board structure inversely provided with a chip. The structure comprises a...
2016/0351481 ELECTRONIC COMPONENT PACKAGE INCLUDING ELECTRONIC COMPONENT, METAL MEMBER, AND SEALING RESIN
An electronic component package according to one aspect of the present disclosure includes a metal pattern layer having a first principal surface and a second...
2016/0351480 SEMICONDUCTOR MODULE AND DRIVE DEVICE EQUIPPED WITH SEMICONDUCTOR MODULE
Provided is a semiconductor module having an integrated insulating sheet structure, wherein detachment of the insulating sheet can be suppressed and improved...
2016/0351479 MOLDED MODULE
An object of this invention is to obtain a molded module with which improvements are achieved in the packaging ability and heat dissipation performance of an...
2016/0351478 POWER MODULE
A power module includes a substrate, a first sub-module and a second sub-module. Each of the first sub-module and the second sub-module includes a...
2016/0351477 PACKAGE FOR A SURFACE-MOUNT SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A method for manufacturing a surface-mount electronic device includes making a first partial cut from a bottom of an assembly that includes a first...
2016/0351476 PROCESS FOR MANUFACTURING A SURFACE-MOUNT SEMICONDUCTOR DEVICE, AND CORRESPONDING SEMICONDUCTOR DEVICE
A process for manufacturing surface-mount semiconductor devices, in particular of the Quad-Flat No-Leads Multi-Row type, comprising providing a metal...
2016/0351475 SEMICONDUCTOR DEVICE INCLUDING LEAD FRAMES WITH DOWNSET
A semiconductor device includes a planar first lead frame including a die pad, a semiconductor chip coupled to the die pad, and a second lead frame coupled to...
2016/0351474 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
A semiconductor device includes: a semiconductor substrate; a wiring layer provided on a front-surface side of the semiconductor substrate; a through-via that...
2016/0351473 SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate, a device layer located at an upper surface of the semiconductor substrate, an insulating layer...
2016/0351472 INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
An integrated circuit device is provided as follows. A connection terminal is disposed on a first surface of a semiconductor structure. A conductive pad is...
2016/0351471 METHOD FOR MANUFACTURING COMPONENT BUILT-IN SUBSTRATE
A substrate is disclosed, which can remove heat from a stacked body of semiconductor elements through a phase change of a coolant. The substrate of the...
2016/0351470 BASE WITH HEAT ABSORBER AND HEAT DISSIPATING MODULE HAVING THE BASE
An exemplary base includes a heat absorber and clips attached to the heat absorber. The heat absorber includes a top surface and a bottom surface. A pair of...
2016/0351469 SEMICONDUCTOR DEVICE
In a semiconductor device, a first to a sixth switching elements are joined to a second main surface of a substrate with their electrode surfaces facing the...
2016/0351468 INTEGRATED PACKAGING OF MULTIPLE DOUBLE SIDED COOLING PLANAR BOND POWER MODULES
An integrated double sided cooled power module has one or multiple phase legs configuration including one or more planar power packages, each planar power...
2016/0351467 LIMITING ELECTRONIC PACKAGE WARPAGE
An electronic package includes a carrier, semiconductor chip, a lid, and a lid-ring. The carrier includes a top surface and a bottom surface configured to be...
2016/0351466 Semiconductor Structure Having Thermal Backside Core
A semiconductor structure includes a semiconductor substrate having a recess disposed beneath a semiconductor device. The semiconductor structure also includes...
2016/0351465 ASSEMBLY LAYER STRUCTURE USED IN TOUCH CONTROL INTEGRATED CIRCUIT (IC) MODULE AND MANUFACTURING METHOD THEREOF
An assembly layer structure applicable to a touch control integrated circuit (IC) module and manufacturing method thereof are described. The assembly layer...
2016/0351464 SEMICONDUCTOR DEVICE PACKAGE
A semiconductor device package which decrease deterioration on characteristics of the chip is provided. The semiconductor device package includes a chip having a...
2016/0351463 PACKAGE STRUCTURES AND METHODS OF FORMING THE SAME
Package structures and methods of forming the same are disclosed. A package structure includes a die, a dielectric layer, an encapsulant and a plurality of...
2016/0351462 FAN-OUT WAFER LEVEL PACKAGE AND FABRICATION METHOD THEREOF
A semiconductor package includes a semiconductor die having an active face. At least one pad is disposed on the active face of the semiconductor die. A molding...
2016/0351461 EPOXY RESIN COMPOSITION FOR ENCAPSULATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE ENCAPSULATED BY THE SAME
An epoxy resin composition for encapsulating a semiconductor device and a semiconductor device encapsulated by the epoxy resin composition, the composition...
2016/0351460 PACKAGE STRUCTURE
A package structure includes a substrate, at least one electronic component, a housing and at least one strut. The at least one electronic component is...
2016/0351459 EMBEDDED ELECTRONIC PACKAGING AND ASSOCIATED METHODS
An electronic package includes a semiconductor die, conductive pillars extending outwardly from the semiconductor die, and a liquid crystal polymer (LCP) body...
2016/0351458 ION IMPLANTATION METHODS AND STRUCTURES THEREOF
A method for fabricating a semiconductor device using a high-temperature ion implantation process includes providing a substrate including a plurality of fins....
2016/0351457 LIGHT EMITTING DIODE DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF
A manufacturing method of a light emitting diode (LED) display device includes forming at least one sub-pixel circuit on a substrate, forming a primary...
2016/0351456 TEST PATTERN STRUCTURE FOR MONITORING SEMICONDUCTOR FABRICATION PROCESS
A test pattern structure includes a substrate, a first layer formed over the substrate and including a plurality of box-shaped portions, and a second layer...
2016/0351455 METHODS OF REVISING OVERLAY CORRECTION DATA
Provided are methods of generating and revising overlay correction data, a method of performing a photolithography process using the overlay correction data,...
2016/0351454 SILICON-GERMANIUM FIN FORMATION
Forming a set of semiconductor fins is disclosed. Forming the set of semiconductor fins can include forming a base structure including a silicon substrate, an...
2016/0351453 METHOD AND STRUCTURE FOR FORMATION OF REPLACEMENT METAL GATE FIELD EFFECT TRANSISTORS
Embodiments of the present invention provide a process that maintains a "keep cap" metal nitride layer on PFET devices within a CMOS structure. The keep cap...
2016/0351452 METHOD OF PATTERNING DOPANT FILMS IN HIGH-K DIELECTRICS IN A SOFT MASK INTEGRATION SCHEME
A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly...
2016/0351451 Methods and Apparatus for MOS Capacitors in Replacement Gate Process
Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor...
2016/0351450 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate, a metal member, and a metal oxide film. The semiconductor substrate is provided with a through-hole...
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