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Patent # Description
2016/0350249 DATA MANAGEMENT FOR ELECTRICAL AND FIBER OPTIC INTERFACES
Some embodiments provide an apparatus that includes a first interface, a second interface, and a data management module. The first interface is configured for...
2016/0350248 METHODS AND APPARATUS FOR A MULTIPLE MASTER BUS PROTOCOL
Embodiments of the invention provide systems, methods, and apparatus for arbitrating a multi-master computer bus. The embodiments include a multi-master serial...
2016/0350247 LATENCY IMPROVEMENTS ON A BUS USING MODIFIED TRANSFERS
Techniques for latency improvement are described herein. The techniques may include an apparatus having a receiver configured to receive transfers over a bus....
2016/0350246 Method And Apparatus For Split Burst Bandwidth Arbitration
An embedded system and method for controlling such are disclosed. The embedded system includes a direct memory controller comprising a plurality of channels,...
2016/0350245 WORKLOAD BATCH SUBMISSION MECHANISM FOR GRAPHICS PROCESSING UNIT
Technologies for submitting programmable workloads to a graphics processing unit include a computing device to prepare a batch submission of the programmable...
2016/0350244 MEMORY SHARING FOR DIRECT MEMORY ACCESS BY A DEVICE ASSIGNED TO A GUEST OPERATING SYSTEM
A guest operating system (OS) detects a direct memory access (DMA) write request for a device assigned to a guest OS to perform a DMA write to a page of memory...
2016/0350243 SEMICONDUCTOR DEVICE
A semiconductor device in which, in principle, plural interrupt request signals can be inputted to a single interrupt terminal is provided. In the...
2016/0350242 METHOD AND APPARATUS FOR PROCESSING ADAPTIVE INTERRUPT, HOST EMPLOYING THE SAME, I/O DEVICE AND SYSTEM
Processing an adaptive interrupt includes selectively setting an input/output (I/O) device in a computing system to an adaptive masking mode when at least one...
2016/0350241 INFORMATION PROCESSING APPARATUS AND DATA TRANSFER METHOD
An information processing apparatus includes a first, second, and third chips connected in series. The second chip includes a receiving unit, a register, a...
2016/0350240 SERIAL PERIPHERAL INTERFACE HOST PORT
A serial peripheral interface (SPI) host port is disclosed that enables a host external to a processor to access the processor's memory-mapped resources using...
2016/0350239 Method for resolving a cable mismatch in a target device
A method for method for resolving a cable mismatch by a target device is provided. The method includes determining that all PHYs in a receptacle are currently...
2016/0350238 Backup Accessible By Subset Of Related Devices
Some embodiments provide, for a particular device in a set of related devices, a method for backing up data synchronized between the devices. The method...
2016/0350237 MANAGING SECTORED CACHE
Apparatus, systems, and methods to manage memory operations are described. In one example, a controller comprises logic to receive a first transaction to...
2016/0350236 MEMORY SWAP FOR DIRECT MEMORY ACCESS BY A DEVICE ASSIGNED TO A GUEST OPERATING SYSTEM
A hypervisor detects a page fault associated with the request for a device assigned to a guest operating system to perform direct memory access (DMA) of a...
2016/0350235 EXIT-LESS MOVEMENT OF GUEST MEMORY ASSIGNED TO A DEVICE IN A VIRTUALIZED ENVIRONMENT
Embodiments of the disclosure enable exit-less movement of guest memory assigned to a device in a virtualized environment. An example method comprises...
2016/0350234 MULTI-THREADED TRANSLATION AND TRANSACTION RE-ORDERING FOR MEMORY MANAGEMENT UNITS
Systems and methods relate to performing address translations in a multithreaded memory management unit (MMU). Two or more address translation requests can be...
2016/0350233 ZERO COPY MEMORY RECLAIM FOR APPLICATIONS USING MEMORY OFFLINING
An application sends a first request to an operating system to provide a hardware device with direct memory access to contents of a virtual memory location in...
2016/0350232 MEMORY SYSTEM ARCHITECTURE
Provided are methods, systems, and apparatus for managing and controlling memory caches, in particular, system level caches outside of those closest to the...
2016/0350231 MAGNETIC DISK DEVICE AND METHOD FOR EXECUTING SYNCHRONIZE COMMAND
According to one embodiment, a magnetic disk device includes a disk, a volatile memory, and a controller. The disk includes a save area and a user data area....
2016/0350230 APPARATUSES AND METHODS FOR COMPUTE ENABLED CACHE
The present disclosure includes apparatuses and methods for compute enabled cache. An example apparatus comprises a compute component, a memory and a...
2016/0350229 DYNAMIC CACHE REPLACEMENT WAY SELECTION BASED ON ADDRESS TAG BITS
A cache memory comprising: a mode input indicates in which of a plurality of allocation modes the cache memory is to operate; a set-associative array of...
2016/0350228 CACHE REPLACEMENT POLICY THAT CONSIDERS MEMORY ACCESS TYPE
An associative cache memory, comprising: an array of storage elements arranged as M sets by N ways; an allocation unit allocates the storage elements in...
2016/0350227 CACHE MEMORY BUDGETED BY CHUNKS BASED ON MEMORY ACCESS TYPE
A set associative cache memory, comprising: an array of storage elements arranged as M sets by N ways, each set belongs in one of L mutually exclusive groups;...
2016/0350226 IN-MEMORY CACHING WITH ON-DEMAND MIGRATION
For on-demand migration of data in a distributed memory storage configuration, an identifier is transformed at a client into a transformed identifier. From a...
2016/0350225 SPECULATIVE PRE-FETCH OF TRANSLATIONS FOR A MEMORY MANAGEMENT UNIT (MMU)
Systems and methods for pre-fetching address translations in a memory management unit (MMU) are disclosed. The MMU detects a triggering condition related to...
2016/0350224 PATTERN DETECTOR FOR DETECTING HANGS
A microprocessor comprises a cache including a tag array; a tag pipeline that arbitrates access to the tag array; and a pattern detector. The pattern detector...
2016/0350223 LOGIC ANALYZER FOR DETECTING HANGS
A microprocessor comprises a cache including a tag array; a tagpipe that arbitrates access to the tag array; and a logic analyzer for investigating a...
2016/0350222 PROVIDING MEMORY MANAGEMENT UNIT (MMU) PARTITIONED TRANSLATION CACHES, AND RELATED APPARATUSES, METHODS, AND...
Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, in one...
2016/0350221 System, Method, and Apparatus for Improving Throughput of Consecutive Transactional Memory Regions
Systems, apparatuses, and methods for improving TM throughput using a TM region indicator (or color) are described. Through the use of TM region indicators...
2016/0350220 CACHE COHERENCY
A cache coherency controller comprises a directory indicating, for memory addresses cached by one or more of a group of one or more cache memories connectable...
2016/0350219 CACHE COHERENCY
A cache coherency controller comprises a directory indicating, for memory addresses cached by a group of two or more cache memories in a coherent cache...
2016/0350218 PERSISTENT MEMORY CONTROLLER BASED ATOMICITY ASSURANCE
According to an example, PM controller based atomicity assurance may include receiving data that is related to an application for storage in a PM. PM...
2016/0350217 APPARATUSES AND METHODS FOR PROVIDING DATA CONSISTENCY MESSAGING FOR SHARED MEMORY SYSTEMS
Apparatuses and methods for providing data consistency messaging for shared memory systems are disclosed herein. An example apparatus may include a producer...
2016/0350216 METHOD AND APPARATUS FOR CACHE MANAGEMENT OF TRANSACTION PROCESSING IN PERSISTENT MEMORY
The present invention provides a method and an apparatus for cache management of transaction processing in persistent memory. The method includes: when a...
2016/0350215 DISTRIBUTED HANG RECOVERY LOGIC
A microprocessor comprises a plurality of queues containing transient transaction state information about cache-accessing transactions; a plurality of...
2016/0350214 IDLE TIME SOFTWARE GARBAGE COLLECTION
A computing device schedules software garbage collection for software applications during processor idle periods. A future idle period of time during which a...
2016/0350213 ANALYTICS BASED CONTROL OF THIN PROVISIONING ENVIRONMENT
Data storage using application storage analytics that: (i) runs a set of application(s) that use a thin provision data storage device for data storage; (ii)...
2016/0350212 APPLICATION PROCESSOR AND A MOBILE APPARATUS HAVING A PLURALITY OF ADDRESS MAPPING FORMATS AND METHOD OF...
An application processor and a mobile apparatus are provided. The application processor includes a memory device configured to store data based upon a...
2016/0350211 WHITEBOX NETWORK FUZZING
Software testing of networked devices using whitebox fuzzing is provided. Target network device (TC) can execute a software target that can selectively receive...
2016/0350210 DETECTING ERROR STATES WHEN INTERACTING WITH WEB APPLICATIONS
Detecting error states when interacting with web applications is performed by accessing a first web page of a web application, determining that the first web...
2016/0350209 Selective Bypass of Code Flows in Software Program
Embodiments relate to systems and methods allowing selective bypass of code flows in computer software. According to particular embodiments, a bypass attribute...
2016/0350208 GENERATING TEST SCRIPTS THROUGH APPLICATION INTEGRATION
Provided are techniques for parsing a pre-existing test script for a graphical user interface (GUI) to identify a first GUI action in a first line of the...
2016/0350207 GENERATION OF TEST SCENARIOS BASED ON RISK ANALYSIS
Embodiments include a method for generation of test scenarios based on risk analysis. The method includes receiving a first set of code test scenarios, the...
2016/0350206 EMPLOYING CODE OVERLAYS TO FACILITATE SOFTWARE DEVELOPMENT
In one embodiment, a method for editing and testing computer programming code is provided. The method includes receiving a first file comprising computer...
2016/0350205 CONCURRENT EXECUTION OF A FIRST INSTANCE AND A CLONED INSTANCE OF AN APPLICATION
Methods, systems, and apparatus, including computer program products, for reconciling data on a set of virtual machines, generating a virtual machine snapshot...
2016/0350204 SYSTEM AND METHOD FOR PROVIDING AUTOMATED COMPUTER LANGUAGE TRANSLATION AND VERIFICATION
Systems, methods, and other embodiments are disclosed that are configured to verify the translation of a program from a first programming language to a second...
2016/0350203 Identifying Cause of Incidents in the DevOps Environment Automatically
In one aspect, a method for identifying software development teams causing operation incidents when changing and deploying code is provided. The method...
2016/0350202 METHOD AND APPARATUS FOR FINDING BUGS IN COMPUTER PROGRAM CODES
A method for debugging program code is performed at an apparatus having one or more processors and memory for storing programs to be executed by the one or...
2016/0350201 ETL DATA FLOW DESIGN ASSISTANCE THROUGH PROGRESSIVE CONTEXT MATCHING
The present disclosure provides a method and apparatus for re-using existing data flow design jobs in a data integration design environment (IDE). An example...
2016/0350200 PERFORMANCE ENHANCEMENT MODE SELECTION TOOL
A computer-implemented method of reducing impact of performance data gathering on execution of instrumented code comprises gathering respective performance...
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