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Patent # Description
2016/0359039 INTEGRATED TERMINATION FOR MULTIPLE TRENCH FIELD PLATE
A semiconductor device includes a vertical MOS transistor with a plurality of parallel RESURF drain trenches separated by a constant spacing in a vertical...
2016/0359038 LOCAL THINNING OF SEMICONDUCTOR FINS
After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a...
2016/0359037 GERMANIUM DUAL-FIN FIELD EFFECT TRANSISTOR
In one example, a field effect transistor includes a pair of fins positioned in a spaced apart relation. Each of the fins includes germanium. Source and drain...
2016/0359036 REDUCED RESISTANCE SHORT-CHANNEL InGaAs PLANAR MOSFET
A metal-oxide-semiconductor field effect transistor (MOSFET) and a method of fabricating a MOSFET are described. The method includes depositing and patterning...
2016/0359035 SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME
A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is over the first III-V compound layer and is different from the...
2016/0359034 HIGH ELECTRON MOBILITY TRANSISTORS
The present disclosure relates to a transistor device having a donor bi-layer configured to provide low-resistance to source and drain contacts while...
2016/0359033 COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A compound semiconductor device includes: a compound semiconductor layered structure; a gate electrode formed above the compound semiconductor layered...
2016/0359032 COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A compound semiconductor device includes: a carrier transit layer; a carrier supply layer that is formed over the carrier transit layer and is made of InAlN;...
2016/0359031 Gateless Switch with Capacitively-Coupled Contacts
A switch includes an input contact and an output contact to a conducting channel. At least one of the input and output contacts is capacitively coupled to the...
2016/0359030 Enhancement Mode III-N HEMTs
A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access...
2016/0359029 POWER MOSFET HAVING PLANAR CHANNEL, VERTICAL CURRENT PATH, AND TOP DRAIN ELECTRODE
In one embodiment, a power MOSFET cell includes an N+ silicon substrate having a drain electrode. An N-type drift layer is grown over the substrate. An N-type...
2016/0359028 SEMICONDUCTOR DEVICE
In a back surface hole injection type diode, by more effectively securing the effect of hole injection from the back surface of a semiconductor substrate, the...
2016/0359027 SEMICONDUCTOR DEVICE
A semiconductor device includes an IGBT region with a bottom-body region on a front surface side of an IGBT drift region, an IGBT barrier region on a front...
2016/0359026 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device including an IGBT element having features of a low on-state voltage and a low turn-off loss is provided. The semiconductor device is...
2016/0359025 INSULATED GATE BIPOLAR TRANSISTOR (IGBT) AND RELATED METHODS
An insulated gate bipolar transistor (IGBT) includes a gate trench, an emitter trench, and an electrically insulative layer coupled to the emitter trench and...
2016/0359024 Method Of Forming Split Gate Memory Cells With 5 Volt Logic Devices
A method of forming a memory device on a semiconductor substrate having a memory region (with floating and control gates), a first logic region (with first...
2016/0359023 SILICON GERMANIUM-ON-INSULATOR FORMATION BY THERMAL MIXING
A layer of amorphous silicon is formed on a germanium-on-insulator substrate, or a layer of germanium is formed on a silicon-on-insulator substrate. An anneal...
2016/0359022 GERMANIUM DUAL-FIN FIELD EFFECT TRANSISTOR
In one example, a field effect transistor includes a pair of fins positioned in a spaced apart relation. Each of the fins includes germanium. Source and drain...
2016/0359021 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
Methods of forming an integrated circuit device are provided. The methods may include forming a gate structure on a substrate, forming a first etch mask on a...
2016/0359020 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
A method for manufacturing a semiconductor device includes forming a fin structure extending in a first direction on a substrate, forming a sacrificial gate...
2016/0359019 SEMICONDUCTOR DEVICE INCLUDING STRAINED FINFET
A semiconductor device includes at least one semiconductor fin on an upper surface of a base substrate. The at least one semiconductor fin includes a strained...
2016/0359018 SPLIT GATE SEMICONDUCTOR DEVICE WITH CURVED GATE OXIDE PROFILE
A split gate semiconductor device includes a trench gate having a first electrode region and a second electrode region that are separated from each other by a...
2016/0359017 METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING TRENCH WALLS HAVING MULTIPLE SLOPES
A semiconductor device includes a gate spacer defining a trench. The trench includes a first part and a second part sequentially positioned on a substrate. An...
2016/0359016 TRANSISTOR WITH CONTACTED DEEP WELL REGION
Various methods and devices that involve body contacted transistors are disclosed. An exemplary method comprises forming a gate on a planar surface of a...
2016/0359015 METHOD OF FORMING A HIGH ELECTRON MOBILITY TRANSISTOR
A method of forming a high electron mobility transistor (HEMT) includes forming a second III-V compound layer on a first III-V compound layer, forming a source...
2016/0359014 Methods for Forming a Plurality of Semiconductor Devices on a Plurality of Semiconductor Wafers
A method for forming a plurality of semiconductor devices on a plurality of semiconductor wafers is provided. The method includes forming an electrically...
2016/0359013 LATERAL BIPOLAR TRANSISTOR
A bipolar junction transistor comprises a semiconductor layer disposed on an insulating material, at least a portion of the semiconductor layer forming a base...
2016/0359012 SEMICONDUCTOR DEVICE BLOCKING LEAKAGE CURRENT AND METHOD OF FORMING THE SAME
A semiconductor device includes a gate assembly disposed on a device isolation layer, a gate spacer disposed on a side surface of the gate assembly, a contact...
2016/0359011 Techniques for Multiple Gate Workfunctions for a Nanowire CMOS Technology
In one aspect, a method of forming a CMOS device with multiple transistors having different Vt's is provided which includes: forming nanowires and pads on a...
2016/0359010 SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHOD
The semiconductor device structures and methods for forming the same are provided. The semiconductor device structure includes a metal gate over a substrate. A...
2016/0359009 METHODS OF FORMING A GATE CONTACT ABOVE AN ACTIVE REGION OF A SEMICONDUCTOR DEVICE
One method disclosed herein includes, among other things, forming a gate contact opening in a layer of insulating material, wherein the gate contact opening is...
2016/0359008 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device includes forming active fins on a substrate; forming source/drain regions on the active fins on both sides of...
2016/0359007 SILICON CARBIDE SUBSTRATE, SEMICONDUCTOR DEVICE AND METHODS FOR MANUFACTURING THEM
A silicon carbide substrate capable of reducing on-resistance and improving yield of semiconductor devices is made of single-crystal silicon carbide, and...
2016/0359006 Integrated Circuit On Corrugated Substrate
By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a "corrugated substrate"), the resolution limitations associated...
2016/0359005 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate, an initial layer, and a superlattice stack. The initial layer is located on the substrate and includes aluminum...
2016/0359004 STRESS CONTROL FOR HETEROEPITAXY
Stress control using superlattice structures for epitaxy on base wafer substrates, including AlN/GaN superlattices for epitaxy of GaN on silicon {111}...
2016/0359003 STRAIN RELEASE IN PFET REGIONS
A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a...
2016/0359002 Semiconductor-On-Insulator With Back Side Heat Disspation
Embodiments of the present invention provide for the enhancement of transistors in a semiconductor structure using a strain layer. The structure comprises a...
2016/0359001 SILICON GERMANIUM FIN
A method includes forming a multilayered stack on a surface of a supporting layer. The multilayered stack is composed of alternating layers of compressively...
2016/0359000 METHOD OF FORMING GUARD RING STRUCTURE
A method of making a circuit device includes forming core circuitry. The core circuitry includes a doped region in the core circuit. The method further...
2016/0358999 Capacitors in Integrated Circuits and Methods of Fabrication Thereof
A capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first...
2016/0358998 SEMICONDUCTOR DEVICE INCLUDING A CAPACITOR
A capacitor in a semiconductor device may include a lower electrode, a dielectric layer including a metal oxide and disposed on the lower electrode, a first...
2016/0358997 DISPLAY MODULE, DISPLAY APPARATUS FOR VEHICLE, AND METHOD OF MANUFACTURING THE SAME
A display module includes abase substrate including an upper surface and a lower surface opposite the upper surface; a pixel layer facing the base substrate...
2016/0358996 OLED DISPLAY PANEL AND MANUFACTURING METHOD THEREOF
OLED display panel is provided which can control the problem of shedding even in high definition panels. Metal wiring 5 which conducts with an earth line of a...
2016/0358995 ORGANIC LIGHT EMITTING DIODE DISPLAY
An organic light emitting diode display includes a substrate, a scan line on the substrate for transferring a scan signal, a data line crossing the scan line...
2016/0358994 DISPLAY APPARATUS, MANUFACTURING METHOD OF DISPLAY APPARATUS, AND ELECTRONIC DEVICE
A display apparatus including: a display region provided with a plurality of pixel portions; wires installed to the respective pixel portions within the...
2016/0358993 PIXEL STRUCTURE AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE, DISPLAY DEVICE
A pixel structure and a manufacturing method thereof, an array substrate and a display device are disclosed, which relate to display technology and solve the...
2016/0358992 Organic Light Emitting Display Device and Method for Manufacturing the Same
The organic light emitting display device includes a flexible substrate, a thin-film transistor on the flexible substrate, a first anode on the thin-film...
2016/0358991 ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY APPARATUS
The present invention provides an array substrate and a manufacturing method thereof, and a display apparatus; and it relates to the field of display. The...
2016/0358990 LIGHT EMITTING DISPLAY APPARATUS
There is provided a light emitting display apparatus including at least a light emitting element and a thin film transistor (TFT) for driving the light...
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