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Patent # Description
2016/0358939 DISPLAY APPARATUS
A display apparatus includes: a first substrate including a display area and a non-display area adjacent to the display area; a second substrate facing the...
2016/0358938 DISPLAY DEVICE AND FABRICATION METHOD THEREOF
A display device having a display area and a non-display area includes a substrate, a pixel at the display area, a signal line on the substrate and...
2016/0358937 Array Substrate and Manufacturing Method Thereof and Display Panel
An array substrate and manufacturing method thereof and a display panel are disclosed. The manufacturing method of an array substrate includes: forming...
2016/0358936 NON-VOLATILE MEMORY DEVICE
A non-volatile memory device includes a conductive layer, a first electrode layer provided side by side with the conductive layer in a first direction, a...
2016/0358935 SEMICONDUCTOR MEMORY DEVICE AND PRODUCTION METHOD THEREOF
A semiconductor memory device according to an embodiment comprises a memory cell array including a stacked body and a semiconductor film, the stacked body...
2016/0358934 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
Provided is a fabricating method of a semiconductor device, including the following. Fin structures are formed on a substrate, and the adjacent fin structures...
2016/0358933 METHOD OF MAKING A THREE-DIMENSIONAL MEMORY DEVICE HAVING A HETEROSTRUCTURE QUANTUM WELL CHANNEL
A cylindrical confinement electron gas confined within a two-dimensional cylindrical region can be formed in a vertical semiconductor channel extending through...
2016/0358932 GATE-ALL-AROUND VERTICAL GATE MEMORY STRUCTURES AND SEMICONDUCTOR DEVICES, AND METHODS OF FABRICATING...
Present example embodiments relate generally to methods of fabricating a three-dimensional gate-all-around vertical gate semiconductor structure comprising...
2016/0358931 METHODS OF FABRICATING EMBEDDED ELECTRONIC DEVICES INCLUDING CHARGE TRAP MEMORY CELLS
A method of fabricating an embedded electronic device including charge trap memory cells that includes forming a tunnel insulation layer, a charge trap layer...
2016/0358930 WING-TYPE PROJECTION BETWEEN NEIGHBORING ACCESS TRANSISTORS IN MEMORY DEVICES
A flash memory device is disposed on a semiconductor substrate. The flash memory device includes flash memory cells arranged in rows and columns. Respective...
2016/0358929 MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE
A manufacturing method of a semiconductor memory device is provided. The semiconductor memory device can suppress current leakage generated during a...
2016/0358928 SELF-ALIGNED FLASH MEMORY DEVICE WITH WORD LINE HAVING REDUCED HEIGHT AT OUTER EDGE OPPOSITE TO GATE STACK
The present disclosure relates to a flash memory device, and associated methods. In some embodiments, the flash memory device has a gate stack with a control...
2016/0358927 MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A memory device, including a first memory region including a first substrate, a plurality of first semiconductor devices on the first substrate, and a first...
2016/0358926 FinFETs with Different Fin Heights
An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device...
2016/0358925 SEMICONDUCTOR DEVICE HAVING STRESSOR AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower...
2016/0358924 SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR
An IC may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a...
2016/0358923 MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
A memory device that is as small in area as possible and has an extremely long data retention period. A transistor with extremely low leakage current is used...
2016/0358922 METHOD AND STRUCTURE TO FORM TENSILE STRAINED SIGE FINS AND COMPRESSIVE STRAINED SIGE FINS ON A SAME SUBSTRATE
A method of forming a semiconductor structure that includes compressive strained silicon germanium alloy fins having a first germanium content and tensile...
2016/0358921 SEMICONDUCTOR DEVICE HAVING MULTIWORK FUNCTION GATE PATTERNS
A semiconductor device includes a semiconductor substrate having a first area and a second area, and a first gate pattern on the first area and a second gate...
2016/0358920 SEMICONDUCTOR DEVICE INCLUDING TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES
A semiconductor device includes first through fourth areas, first through fourth gate stacks, the first gate stack includes a first high-dielectric layer, a...
2016/0358919 METHOD FOR FORMING HIGH VOLTAGE TRANSISTOR
A method for forming a high voltage transistor is provided. First, a substrate having a top surface is provided, following by forming a thermal oxide layer on...
2016/0358918 Electronic Devices and Systems, and Methods for Making and Using the Same
Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing...
2016/0358917 COMPACT GUARD RING STRUCTURE FOR CMOS INTEGRATED CIRCUITS
An integrated circuit includes an active device formed in a semiconductor layer of a first conductivity type, a first guard ring of the first conductivity type...
2016/0358916 SELF-ALIGNED SOURCE/DRAIN CONTACTS
A semiconductor substrate includes lower source/drain (S/D) regions. A replacement metal gate (RMG) structure is arranged upon the semiconductor substrate...
2016/0358915 FERROELECTRIC FINFET
A semiconductor device includes a semiconductor substrate and a fin positioned above the semiconductor substrate, wherein the fin includes a semiconductor...
2016/0358914 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A semiconductor device includes a first fin-shaped pattern and a second fin-shaped pattern arranged in a row in a direction, a trench between the first...
2016/0358913 SEMICONDUCTOR DEVICE
Semiconductor devices are provided. The semiconductor device includes a first fin portion and a second fin portion arranged on a substrate and extended in a...
2016/0358912 HIGH-IMPLANT CHANNEL SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins...
2016/0358911 BURIED CHANNEL SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins...
2016/0358910 Double-Sided Vertical Semiconductor Device With Thinned Substrate
A vertical semiconductor device is formed in a semiconductor layer having a first surface, a second surface and background doping. A first doped region, doped...
2016/0358909 SYSTEMS AND METHODS FOR INCREASING PACKING DENSITY IN A SEMICONDUCTOR CELL ARRAY
Systems and methods are provided for using and manufacturing a semiconductor device. A semiconductor device comprises an array of transistors, wherein each...
2016/0358908 METHODS OF FORMING V0 STRUCTURES FOR SEMICONDUCTOR DEVICES BY FORMING A PROTECTION LAYER WITH A NON-UNIFORM...
One illustrative method disclosed herein includes, among other things, forming a source/drain contact structure between two spaced-apart transistor gate...
2016/0358907 DEVICES RELATED TO BARRIER FOR METALLIZATION OF GALLIUM BASED SEMICONDUCTOR
Disclosed are structures and methods related to a barrier layer for metallization of a selected semiconductor such as indium gallium phosphide (InGaP). In some...
2016/0358906 SEMICONDUCTOR DEVICE WITH SCHOTTKY DIODE AND MANUFACTURING METHOD THEREOF
A semiconductor device with an embedded schottky diode and a manufacturing method thereof are provided. A semiconductor device having a schottky diode include:...
2016/0358905 COMPOUND SEMICONDUCTOR DEVICES HAVING BURIED RESISTORS FORMED IN BUFFER LAYER
Structures and methods are provided for fabricating a semiconductor device (e.g., III-V compound semiconductor device) having buried resistors formed within a...
2016/0358904 ELECTROSTATIC DISCHARGE PROTECTION DEVICE
An electrostatic discharge (ESD) protection device includes a first trigger element and a first silicon control rectifier (SCR) element. The first trigger...
2016/0358903 Oversized Contacts and Vias in Layout Defined by Linearly Constrained Topology
A rectangular-shaped interlevel connection layout structure is defined to electrically connect a first layout structure in a first chip level with a second...
2016/0358902 Integrated Circuit with Elongated Coupling
An integrated circuit comprises a first layer on a first level. The first layer comprises a set of first lines. The first lines each have a length and a width....
2016/0358901 SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, METHOD FOR GENERATING MASK DATA, MASK AND COMPUTER...
A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The...
2016/0358900 Semiconductor Device and Method of Manufacturing
A semiconductor device includes a first chip, a dielectric layer over the first chip, and a second chip over the dielectric layer. A conductive layer is...
2016/0358899 INTERPOSER FOR A PACKAGE-ON-PACKAGE STRUCTURE
A package-on-package (PoP) structure includes a first die, a second die, and a memory device electrically coupled to the first die and the second die by an...
2016/0358898 METHODS OF MANUFACTURING MULTI DIE SEMICONDUCTOR DEVICE PACKAGES AND RELATED ASSEMBLIES
Methods of making semiconductor device packages may involve attaching a first semiconductor die to a carrier wafer, an inactive surface of the first...
2016/0358897 THREE DIMENSIONAL STRUCTURES WITHIN MOLD COMPOUND
A method including forming at least one passive structure on a substrate by a build-up process; introducing one or more integrated circuit chips on the...
2016/0358896 LIGHT EMITTING DEVICE PACKAGE AND LIGHT EMITTING DEVICE PACKAGE MODULE
Disclosed herein is a light emitting device package and a light emitting device package module. The light emitting device package includes: a base including a...
2016/0358895 POWER SEMICONDUCTOR MODULE
A power semiconductor module includes: a positive arm and a negative arm that are formed by series connection of self-arc-extinguishing type semiconductor...
2016/0358894 Semiconductor Package for Thermal Dissipation
A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed...
2016/0358893 STACKED SEMICONDUCTOR PACKAGES, METHODS FOR FABRICATING THE SAME, AND/OR SYSTEMS EMPLOYING THE SAME
An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first...
2016/0358892 SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME
Provided is a method for manufacturing a semiconductor package, which includes providing a first substrate, providing, over the first substrate, a second...
2016/0358891 OPOSSUM-DIE PACKAGE-ON-PACKAGE APPARATUS
An apparatus including a first package coupled to a second package, wherein each of the first package and the second package has a first side and an opposite...
2016/0358890 DIFFUSION SOLDER BONDING USING SOLDER PREFORMS
A method includes providing a first and a second joining partner each having a first main surface, wherein at least a portion of the first main surfaces of the...
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