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Patent # Description
2016/0358889 DUAL MOLDED STACK TSV PACKAGE
Packages including an embedded die with through silicon vias (TSVs) are described. In an embodiment, a first level die including TSVs is embedded between a...
2016/0358888 3-D Package Having Plurality of Substrates
A package includes an interposer, which includes a first substrate free from through-vias therein, redistribution lines over the first substrate, and a first...
2016/0358887 SEMICONDUCTOR PACKAGE
A semiconductor package includes a package substrate. A first semiconductor chip is mounted on the package substrate. The first semiconductor chip includes a...
2016/0358886 ARRANGEMENT OF MULTIPLE POWER SEMICONDUCTOR CHIPS AND METHOD OF MANUFACTURING THE SAME
A semiconductor power arrangement includes a chip carrier having a first surface and a second surface opposite the first surface. The semiconductor power...
2016/0358885 METHOD OF FABRICATING AN ELECTRONIC PACKAGE
Some example forms relate a method of fabricating an electronic package. The method includes attaching a source wafer that includes micro devices to a target...
2016/0358884 SEMICONDUCTOR CHIP METAL ALLOY THERMAL INTERFACE MATERIAL
Various apparatus and methods are disclosed. In one aspect, a method of manufacturing a thermal interface material on a semiconductor chip is provided. The...
2016/0358883 BUMP FORMING METHOD, BUMP FORMING APPARATUS, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A bump forming method includes: a bonding step of bonding the leading end of a wire extending out of the tip of a bonding tool to a first point (X1); a wire...
2016/0358882 Wafer Bonding Process and Structure
A semiconductor device and a method of fabricating the same are introduced. In an embodiment, one or more passivation layers are formed over a first substrate....
2016/0358881 METHOD FOR BONDING SUBSTRATES
A method for bonding a first substrate with a second substrate, characterized in that the first substrate and/or the second substrate is/are thinned before the...
2016/0358880 SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE, AND WIRE BONDING APPARATUS
A semiconductor device manufacturing method includes: raising and moving a bonding tool, while paying out a wire, in a direction from a second toward a first...
2016/0358879 DISCHARGE EXAMINATION DEVICE, WIRE-BONDING APPARATUS, AND DISCHARGE EXAMINATION METHOD
A discharge examination device for examining discharge of a wire-bonding apparatus that applies a voltage between a torch electrode and a wire to procure the...
2016/0358878 Substrate and Package Structure
According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the...
2016/0358877 SEMICONDUCTOR PACKAGE USING FLIP-CHIP TECHNOLOGY
A semiconductor package is provided. The semiconductor package includes a semiconductor device bonded to a base through a first conductive structure. The...
2016/0358876 Conical-Shaped or Tier-Shaped Pillar Connections
A pillar structure, and a method of forming, for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical...
2016/0358875 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes a first circuit layer, a copper pillar disposed adjacent to the first circuit layer, a second circuit layer and a solder layer....
2016/0358874 SEMICONDUCTOR DEVICE
A semiconductor device capable of inhibiting oxidation of a Cu wiring even in a high temperature operation. The semiconductor device includes a semiconductor...
2016/0358873 SUBSTRATE STRUCTURE, FABRICATION METHOD THEREOF AND CONDUCTIVE STRUCTURE
A substrate structure is provided, which includes: a substrate body having a plurality of conductive pads; an insulating layer formed on the substrate body and...
2016/0358872 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THEREOF
A semiconductor package comprises a semiconductor chip having an active surface with a conductive pad thereon; an electroplated Au--Sn. alloy bump over the...
2016/0358871 Filter and Capacitor Using Redistribution Layer and Micro Bump Layer
An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above...
2016/0358870 MULTI-DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF
A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors....
2016/0358869 SEMICONDUCTOR DEVICE
An object of the present invention is to provide a semiconductor device capable of eliminating unevenness of current distribution in a plane. A semiconductor...
2016/0358868 CONNECTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation...
2016/0358867 Calibration Kits for RF Passive Devices
A method includes measuring a first calibration kit in a wafer to obtain a first performance data. The wafer includes a substrate, and a plurality of...
2016/0358866 PACKAGE SUBSTRATE DIFFERENTIAL IMPEDANCE OPTIMIZATION FOR 25 GBPS AND BEYOND
A package design method is disclosed for the optimization of package differential impedance at data rates of 25 Gb/s and beyond. The method optimizes the...
2016/0358865 WAFER LEVEL PACKAGE AND FABRICATION METHOD THEREOF
A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first...
2016/0358864 SEMICONDUCTOR MODULE
A semiconductor module including an insulated circuit substrate having a substrate, a circuit layer on a front surface of the substrate, and a metal layer on a...
2016/0358863 METHOD OF MANUFACTURING SEMICONDUCTOR CHIP, SEMICONDUCTOR CHIP, AND SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor chip according to an embodiment includes forming on a semiconductor substrate a plurality of etching masks each...
2016/0358862 SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
The present disclosure relates to a semiconductor device package and a manufacturing method thereof. The semiconductor device package includes a carrier, at...
2016/0358861 REGISTRATION MARK FORMATION DURING SIDEWALL IMAGE TRANSFER PROCESS
Methods of forming a registration mark such as an alignment mark or overlay mark during formation of sub-lithographic structures are provided. Methods may...
2016/0358860 CONTACTS TO SEMICONDUCTOR SUBSTRATE AND METHODS OF FORMING SAME
An aspect of the invention includes a method for forming a contact in a dielectric layer over a semiconductor substrate. The method may comprise: forming a...
2016/0358859 REDUCING CONTACT RESISTANCE IN VIAS FOR COPPER INTERCONNECTS
A method of forming an electrical transmission structure that includes forming an opening through an interlevel dielectric layer to expose at least one...
2016/0358858 ELECTRONIC PART EMBEDDED SUBSTRATE AND METHOD OF PRODUCING AN ELECTRONIC PART EMBEDDED SUBSTRATE
An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part,...
2016/0358857 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device is described below that includes a semiconductor substrate, a conductive film mounted on the semiconductor substrate, and an interlayer...
2016/0358856 SEMICONDUCTOR DEVICES
A semiconductor device includes a first power rail, a second power rail, at least one standard cell and at least one power bridge. The first power rail extends...
2016/0358855 NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
A nonvolatile memory device may include a stair-shaped structure including a first interlayer dielectric layer and a memory cell repeatedly stacked. The...
2016/0358854 Etch Stop Layer in Integrated Circuits
An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride...
2016/0358853 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
A semiconductor device includes a silicon nitride film formed above a front surface side of a semiconductor substrate, a first wiring formed above the silicon...
2016/0358852 ELECTRONIC DEVICE INCLUDING MOAT POWER METALLIZATION IN TRENCH
An electronic device is provided. The electronic device includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, circuitry...
2016/0358851 INTEGRATED CIRCUITS INCLUDING ORGANIC INTERLAYER DIELECTRIC LAYERS AND METHODS FOR FABRICATING THE SAME
Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes...
2016/0358850 SEMICONDUCTOR DEVICE INCLUDING LANDING PAD
A semiconductor device includes conductive lines spaced from a substrate, and an insulating spacer structure between the conductive lines and defining a...
2016/0358849 Flexible Interconnects, Systems, And Uses Thereof
Provided herein are flexible interconnects, systems containing one or more flexible interconnects, and textiles including one or more flexible interconnects.
2016/0358848 MICROELECTRONIC PACKAGE HAVING A PASSIVE MICROELECTRONIC DEVICE DISPOSED WITHIN A PACKAGE BODY
A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the...
2016/0358847 PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a...
2016/0358846 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for...
2016/0358845 DUAL ROW QUAD FLAT NO-LEAD SEMICONDUCTOR PACKAGE
Some of the embodiments of the present disclosure provide a Quad Flat No-Lead package comprising: an outer row of outer peripheral leads disposed on an outer...
2016/0358844 FIELD-EFFECT TRANSISTOR STRUCTURE FOR PREVENTING FROM SHORTING
A field-effect transistor(FET) structure for preventing from shorting is disclosed. The field-effect transistor(FET) structure is applying to a power discrete...
2016/0358843 SEMICONDUCTOR DEVICE INCLUDING A CLIP
A semiconductor device includes a lead frame including a die paddle and a lead, a semiconductor chip, and a clip. The semiconductor chip has a first side and a...
2016/0358842 MICRO-HOSES FOR INTEGRATED CIRCUIT AND DEVICE LEVEL COOLING
A heat-dissipating device includes at least one heat-dissipating surface and a micro-sized cooling mechanism formed directly on the heat-dissipating surface by...
2016/0358841 PACKAGE INTEGRATED SYNTHETIC JET DEVICE
Embodiments include a synthetic jet device formed within layers of a package substrate, such as to provide a controlled airflow for sensing or cooling...
2016/0358840 CERAMIC CIRCUIT BOARD
[Problem] To obtain a ceramic circuit substrate having high bonding strength, excellent heat cycle resistance, enhanced reliability of operation as an...
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