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Patent # Description
2016/0358839 COMPOSITES COMPRISED OF ALIGNED CARBON FIBERS IN CHAIN-ALIGNED POLYMER BINDER
A method for enhancing internal layer-layer thermal interface performance and a chip stack of semiconductor chips using the method. The chip stack includes a...
2016/0358838 Semiconductor Power Package and Method of Manufacturing the Same
A semiconductor power package includes a pre-molded chip housing and an electrically conducting chip carrier cast-in-place in the pre-molded chip housing. The...
2016/0358837 PACKAGE MODULE, STACK STRUCTURE OF PACKAGE MODULE, AND FABRICATING METHODS THEREOF
A package module includes a power module, a first thermal dissipating component and a packaging plastic. The power module includes a substrate and at least one...
2016/0358836 CHIP MODULE WITH STIFFENING FRAME AND ORTHOGONAL HEAT SPREADER
An integrated circuit (IC) chip module includes a carrier, a stiffening frame, an IC chip, and a first directional heat spreader. A second directional heat...
2016/0358835 METHODS FOR SEMICONDUCTOR PASSIVATION BY NITRIDATION AFTER OXIDE REMOVAL
In some embodiments, a semiconductor surface may be effectively passivated by nitridation, preferably using hydrazine, a hydrazine derivative, or a combination...
2016/0358834 SEMICONDUCTOR PACKAGE INCLUDING BARRIER MEMBERS AND METHOD OF MANUFACTURING THE SAME
A semiconductor package can include a semiconductor chip on a substrate inside the semiconductor package and an electrode pad spaced apart from the...
2016/0358833 SEMICONDUCTOR APPARATUS, STACKED SEMICONDUCTOR APPARATUS, ENCAPSULATED STACKED-SEMICONDUCTOR APPARATUS, AND...
The present invention is a semiconductor apparatus including a semiconductor device, an on-semiconductor-device metal pad and a metal interconnect each...
2016/0358832 CERAMIC PACKAGE AND MANUFACTURING METHOD THEREFOR
In a ceramic package, a seal ring is brazed to a substrate portion. A joint portion of the seal ring includes: a metallization layer; a first plating layer...
2016/0358831 MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING SUCH DEVICES
Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly...
2016/0358830 Digital Processing Equipment
An apparatus includes a spray module with at least one column of spray nozzles. Each spray nozzle is configured to deliver a processing substance on a...
2016/0358829 SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD
An apparatus includes: measurement flow passage portions as part of a respective plurality of supply paths of fluids to be supplied to a substrate, the...
2016/0358828 Handle Substrate of Composite Substrate for Semiconductor, and Composite Substrate for Semiconductor
A handle substrate of a composite substrate for a semiconductor includes a base substrate comprising a polycrystalline material; and an amorphous layer...
2016/0358827 METHOD OF FORMING FIN-SHAPED STRUCTURE
A method of forming a fin-shaped structure includes the following step. A substrate having a first area and a second area is provided. An epitaxial structure...
2016/0358826 INTEGRATION OF HYBRID GERMANIUM AND GROUP III-V CONTACT EPILAYER IN CMOS
A trench contact epilayer in a semiconductor device is provided. Embodiments include forming trenches through an interlayer dielectric (ILD) over source/drain...
2016/0358825 N-WELL/P-WELL STRAP STRUCTURES
Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more...
2016/0358824 MINIMIZING SHORTING BETWEEN FINFET EPITAXIAL REGIONS
The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in...
2016/0358823 GERMANIUM DUAL-FIN FIELD EFFECT TRANSISTOR
In one example, a field effect transistor includes a pair of fins positioned in a spaced apart relation. Each of the fins includes germanium. Source and drain...
2016/0358822 Bipolar Junction Transistor Formed on Fin Structures
A method of forming a Bipolar Junction Transistor (BJT) includes forming an elongated collector line, forming an elongated emitter line parallel to the...
2016/0358821 THRU-SILICON-VIA STRUCTURES
Stress generation free thru-silicon-via structures with improved performance and reliability and methods of manufacture are provided. The method includes...
2016/0358820 VIA FORMATION USING SIDEWALL IMAGE TRANFER PROCESS TO DEFINE LATERAL DIMENSION
A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using...
2016/0358819 MECHANISMS FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE WITH FEATURE OPENING
A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a semiconductor substrate and forming a...
2016/0358818 Dummy Structure for Chip-on-Wafer-on-Substrate
Apparatus, and methods of manufacture thereof, in which metal is deposited into openings, thus forming a plurality of metal pads, a plurality of...
2016/0358817 Conductive Element Structure and Method
Conductive element structures and methods of manufacture thereof are disclosed. In some embodiments, a method of forming a conductive element in an insulating...
2016/0358816 METHOD FOR FORMING SEMICONDUCTOR STRUCTURE
One or more techniques or systems for forming a semiconductor structure having a gap are provided herein. In some embodiments, a gap is formed between a first...
2016/0358815 RUTHENIUM METAL FEATURE FILL FOR INTERCONNECTS
A method is provided for at least partially filling a feature in a substrate. The method includes providing a substrate containing a feature, depositing a...
2016/0358814 METHOD OF USING A BARRIER-SEED TOOL FOR FORMING FINE PITCHED METAL INTERCONNECTS
A barrier seed tool is configured to clean trenches in a first chamber, line the trenches with a diffusion barrier layer, and form a copper seed layer over the...
2016/0358813 METHOD OF FORMING TRENCHES
A method of forming trenches is provided. A first layer, a second layer and a third layer are formed on the substrate. A patterned third layer with a plurality...
2016/0358812 REDUCING CONTACT RESISTANCE IN VIAS FOR COPPER INTERCONNECTS
A method of forming an electrical transmission structure that includes forming an opening through an interlevel dielectric layer to expose at least one...
2016/0358811 INTERCONNECT STRUCTURE
Various embodiments provide interconnect structures and fabrication methods. A carbon-containing dielectric layer can be formed on a substrate. A protective...
2016/0358810 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
Provided is a method of fabricating a semiconductor device, including the following. A first material layer, a second material layer and a mask layer are...
2016/0358809 SHUTTER DISK FOR PHYSICAL VAPOR DEPOSITION CHAMBER
A shutter disk suitable for shield a substrate support in a physical vapor deposition chamber is provided. In one embodiment, the shutter disk includes a...
2016/0358808 HYBRID 200 MM/300 MM SEMICONDUCTOR PROCESSING APPARATUSES
In one aspect, several apparatuses are described that allow a processing chamber designed for plasma-enhanced chemical vapor deposition on 300 mm wafers to be...
2016/0358807 Method and Apparatus for Preventing the Deformation of a Substrate Supported at its Edge Area
The method and the apparatus prevents the deformation of a substrate, e.g. a wafer, supported with its edge area or periphery at a support or chuck, and also...
2016/0358806 APPARATUS OF SEPARATING FLEXIBLE SUBSTRATE FROM GLASS SUBSTRATE AND MANUFACTURING EQUIPMENT THEREOF
An apparatus of separating a flexible substrate from a glass substrate comprises a cylinder-shaped roller; and a control unit connected to the roller...
2016/0358805 METHOD OF MECHANICAL SEPARATION FOR A DOUBLE LAYER TRANSFER
The present disclosure relates to a method for mechanically separating layers, in particular in a double layer transfer process. The present disclosure relates...
2016/0358804 GRADED IN-SITU CHARGE TRAPPING LAYERS TO ENABLE ELECTROSTATIC CHUCKING AND EXCELLENT PARTICLE PERFORMANCE FOR...
The present disclosure generally relates to processing chamber seasoning layers having a graded composition. In one example, the seasoning layer is a...
2016/0358803 TRANSPARENT ELECTROSTATIC CARRIER
Embodiments described herein provide an electrostatic carrier for transferring a substrate. The electrostatic carrier may have a transparent body. The...
2016/0358802 BIPOLAR MOBILE ELECTROSTATIC CARRIERS FOR WAFER PROCESSING
In one embodiment, there is provided a carrier comprising a top semiconductor layer having isolated positive electrode regions and isolated negative electrode...
2016/0358801 JOINED BODY MANUFACTURING METHOD AND JOINED BODY
In a step (a), a ceramic substrate 12, a brazing material 56including a metal having a large thermal expansion coefficient, a porous body 54 having a smaller...
2016/0358800 CHAMBER APPARATUS AND PROCESSING SYSTEM
A chamber apparatus according to the present invention including a chamber main body including an opening portion in an upper surface; a door that opens/closes...
2016/0358799 PURGE DEVICE AND PURGE METHOD
A purge device includes a supply flow rate adjuster, which adjusts a supply flow rate of a purge gas supplied to a storage container through a supply pipe, and...
2016/0358798 FRONT OPENING WAFER CONTAINER WITH ROBOTIC FLANGE
A front opening wafer container suitable, for large diameter wafers, 300 mm and above, utilizes a removable robotic flange that attaches vertically, without...
2016/0358797 Semiconductor Processing Boat Design with Pressure Sensor
Presented herein is a device processing boat comprising a base and at least one unit retainer disposed in the base. The device further comprises a cover having...
2016/0358796 Cable drive robot mechanism for exchanging samples
Techniques of swapping two samples with a mechanical arm that has no backlash, no friction, no particle contamination are described. With the unique structure...
2016/0358795 METHODS OF PROTOTYPING AND MANUFACTURING WITH CLEANSPACE FABRICATORS
The present invention provides various aspects for processing multiple types of substrates within cleanspace fabricators or for processing multiple or single...
2016/0358794 SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD
A substrate processing apparatus includes a vacuum chamber and a turntable provided in the vacuum chamber. The turntable includes a substrate receiving area...
2016/0358793 PLASMA PROCESSING APPARATUS AND METHOD, AND METHOD OF MANUFACTURING ELECTRONIC DEVICE
In an inductively coupled plasma torch unit, two coils, a first ceramic block, and a second ceramic block are arranged, and an annular chamber is provided....
2016/0358792 GAS SYSTEMS AND METHODS FOR CHAMBER PORTS
An electronic device manufacturing system may include a chamber port assembly that provides an interface between a transfer chamber and a process chamber. In...
2016/0358791 COPPER-CERAMIC BONDED BODY AND POWER MODULE SUBSTRATE
There is a provided a copper-ceramic bonded body in which a copper member formed of copper or a copper alloy and a ceramic member formed of nitride ceramic are...
2016/0358790 Barrier Chemical Mechanical Planarization Slurries Using Ceria-Coated Silica Abrasives
Chemical Mechanical Planarization (CMP) polishing compositions comprising composite particles, such as ceria coated silica particles, offer tunable polishing...
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