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Patent # Description
2016/0357689 Operating System-Managed Interrupt Steering in Multiprocessor Systems
An operating system includes an interrupt router that dynamically steers each interrupt to one or more processors within set of processors based on overall...
2016/0357688 APPARATUS AND METHOD FOR CONTROLLING ACCESS TO A MEMORY DEVICE
An apparatus and method are provided for controlling access to a memory device. The apparatus has a pending access requests storage that is used to store...
2016/0357687 KEY ENCRYPTION AND DECRYPTION
Provided is a data storage drive for encrypting data, comprising a microprocessor and circuitry coupled to the microprocessor and adapted to receive a session...
2016/0357686 Dynamic Cache Allocation Adjustment Using Multiple Cache Simulations for Efficient Cache Utility Curve Construction
The configuration of a cache is adjusted within a computer system that includes at least one entity that submits a stream of references, each reference...
2016/0357685 STORING A SYSTEM-ABSOLUTE ADDRESS (SAA) IN A FIRST LEVEL TRANSLATION LOOK-ASIDE BUFFER (TLB)
Embodiments relate to a method, system and computer program product for storing a system-absolute address (SAA) in a first level look-aside buffer (TLB). In...
2016/0357684 PREEMPTIVE GUEST MERGING FOR VIRTUALIZATION HYPERVISORS
Aspects of the present invention provide a solution for managing memory. A method according to an embodiment includes: prior to any storage of a page in the...
2016/0357683 CACHE MEMORY SYSTEM AND PROCESSOR SYSTEM
A cache memory system includes cache memories of at least one layer, at least one of the cache memories having a data cache to store data and a tag to store an...
2016/0357682 SET SELECTION OF A SET-ASSOCIATIVE STORAGE CONTAINER
A system includes a set-associative storage container and a processor configured to generate a vector that is a random number. Two or more residue functions...
2016/0357681 MULTI-MODE SET ASSOCIATIVE CACHE MEMORY DYNAMICALLY CONFIGURABLE TO SELECTIVELY SELECT ONE OR A PLURALITY OF...
A cache memory stores 2 J-byte cache lines and includes an array of 2 N sets each holding tags each X bits, an input receives a Q-bit memory address,...
2016/0357680 SET ASSOCIATIVE CACHE MEMORY WITH HETEROGENEOUS REPLACEMENT POLICY
A set associative cache memory, comprising: an array of storage elements arranged as M sets by N ways; an allocation unit that allocates the storage elements...
2016/0357679 STORE FORWARDING CACHE
A load request is received to retrieve a piece of data from a location in memory and the load request follows one or more store requests in a set of...
2016/0357678 PREDICTIVE CACHING AND FETCH PRIORITY
Predicting what content items a user finds important and sending those items to a cache on the user's device at times when doing so will not drain resources...
2016/0357677 MULTIPLE DATA PREFETCHERS THAT DEFER TO ONE ANOTHER BASED ON PREFETCH EFFECTIVENESS BY MEMORY ACCESS TYPE
A processor includes a first prefetcher that prefetches data in response to memory accesses and a second prefetcher that prefetches data in response to memory...
2016/0357676 PREFETCH THRESHOLD FOR CACHE RESTORATION
Embodiments relate to a prefetch threshold for cache restoration. An aspect includes determining, based on a task switch from an outgoing task to a current...
2016/0357675 SYSTEM AND METHOD FOR MANAGEMENT OF CACHE CONFIGURATION
Systems and methods for managing cache configurations are disclosed. In accordance with a method, a system management control module may receive access rights...
2016/0357674 Unified Online Cache Monitoring and Optimization
A cache in a computer system is configured with a plurality of monitoring slices, each comprising a separately addressable partition of the cache. With each...
2016/0357673 METHOD OF MAINTAINING DATA CONSISTENCY
A method of maintaining data consistency in a tree, the method including the steps of: storing leaf nodes in non-volatile memory, the leaf nodes comprising...
2016/0357672 METHODS AND APPARATUS FOR ATOMIC WRITE PROCESSING
Example implementations described herein are directed to implementation of the atomic write feature in the storage system setting. Example implementations may...
2016/0357671 SYSTEM AND METHOD FOR REMOVING DATA FROM PROCESSOR CACHES IN A DISTRIBUTED MULTI-PROCESSOR COMPUTER SYSTEM
A processor (600) in a distributed shared memory multi-processor computer system (10) may initiate a flush request to remove data from its cache. A processor...
2016/0357670 POWER-SAFE DATA MANAGEMENT SYSTEM
Embodiments of the invention include systems and methods for recovering the system status and maintaining drive coherency after an unexpected power loss. In...
2016/0357669 FLUSHING CONTROL WITHIN A MULTI-THREADED PROCESSOR
A data processing apparatus 2 performs multi-threaded processing using the processing pipeline 6, 8, 10, 12, 14, 16, 18. Flush control circuitry 30 is...
2016/0357668 PARALLEL CACHING ARCHITECTURE AND METHODS FOR BLOCK-BASED DATA PROCESSING
A multi-processor computer system with shared memory resources includes a first plurality of sensors configured to acquire inertial and positional data related...
2016/0357667 SYSTEM FOR ENABLING CHANNEL DESIGNATION DIFFERENTIATION FOR HIERARCHICALLY ORGANIZING AND ACCESSING ADDRESS...
A system of multiple computer systems operating over a network that creates addresses using elements received by users or determined by administrators or...
2016/0357666 MEMORY INTERLEAVING ON MEMORY CHANNELS
A memory interleaver includes a channel selection unit to receive a system memory address for a memory request. The interleaver also includes a local memory...
2016/0357665 NONVOLATILE MEMORY MODULE AND OPERATION METHOD THEREOF
The nonvolatile memory module includes at least one nonvolatile memory device and a device controller configured to receive a storage command from an external...
2016/0357664 MULTI-MODE SET ASSOCIATIVE CACHE MEMORY DYNAMICALLY CONFIGURABLE TO SELECTIVELY ALLOCATE INTO ALL OR A SUBSET...
A cache stores 2 J-byte cache lines has an array of 2 N sets each holds tags each X bits and 2 W ways. An input receives a Q-bit address, MA[(Q-1):0], having a...
2016/0357663 SOFTWARE DEFECT REPORTING
Provided are approaches for software defect reporting. Specifically, one approach provides identifying a software defect; generating a software defect report,...
2016/0357662 MONITORING AND CAPTURING EARLY DIAGNOSTIC DATA
A deviance monitoring module is provided for examining various parameters of an operating system for deviance from a baseline behavior at specified intervals....
2016/0357661 AUTOMATED DYNAMIC TEST CASE GENERATION
Embodiments of the present invention provide systems and methods for generating a set of test cases using a base test program. The base test program may be...
2016/0357660 EARLY RISK IDENTIFICATION IN DEVOPS ENVIRONMENTS
A computer executes a first version of a code module in a first test environment, collects a first set of execution measurements, and creates a first profile...
2016/0357659 DETECTING MERGE CONFLICTS AND COMPILATION ERRORS IN A COLLABORATIVE INTEGRATED DEVELOPMENT ENVIRONMENT
A method, and associated computer system and computer program product, of detecting source code merge conflicts and compilation errors. Uncommitted changes...
2016/0357658 Implementation Of Processor Trace In A Processor That Supports Binary Translation
In an embodiment, a processor includes execution logic to execute binary translated (BT) code that is translated from native architecture (NA) code. The...
2016/0357657 Methods and Systems for Increased Debugging Transparency
Embodiments herein disclose a debugging framework that employs a mode in the processor (for example, a processor using x86 architecture), to transparently...
2016/0357656 INFORMATION PROCESSING APPARATUS, METHOD, AND COMPUTER READABLE MEDIUM
An acquire an integrated value of count values and first information at every specific timing, the integrated value of count values being acquired by counting...
2016/0357655 PERFORMANCE INFORMATION GENERATING METHOD, INFORMATION PROCESSING APPARATUS AND COMPUTER-READABLE STORAGE...
A performance information generating method, the method includes: reading, by a computer, context information generated by a context information collection...
2016/0357654 SMART ADVICE TO CHARGE NOTIFICATION
Systems and methods are disclosed for advising a user when an energy storage device in a computing system needs charging. State of charge data of the energy...
2016/0357653 SYSTEMS AND METHODS FOR PRE-WARNING A MONITORING TOOL FOR A COMMUNICATION BUS
Systems and methods for pre-warning a monitoring tool for a communication bus are disclosed. In exemplary aspects, a monitoring tool is coupled to a...
2016/0357652 MULTIPLE POINTS IN TIME DISK IMAGES FOR DISASTER RECOVERY
An enterprise disaster recovery system, including at least one data disk, a processor for running at least one data application that reads data from the at...
2016/0357651 SYSTEM ON CHIP WITH DEBUG CONTROLLER AND OPERATING METHOD THEREOF
A System on Chip (SOC) is disclosed. The SOC comprises a first UART controller, a second UART controller, a debug controller, a processor, a UART port, a first...
2016/0357650 DYNAMIC CACHE ROW FAIL ACCUMULATION DUE TO CATASTROPHIC FAILURE
A technique is provided for accumulating failures. A failure of a first row is detected in a group of array macros, the first row having first row address...
2016/0357649 SYSTEM AND METHOD FOR MANAGING RAID STORAGE SYSTEM HAVING A HOT SPARE DRIVE
A method provides rebuilding data in a hot spare storage device when multiple storage devices fail in a storage system. The method includes a storage...
2016/0357648 DYNAMIC MIRRORING
One or more techniques and/or systems are provided for dynamic mirroring. A first storage node and the second storage node within a first storage cluster may...
2016/0357647 COMPUTER, HYPERVISOR, AND METHOD FOR ALLOCATING PHYSICAL CORES
A computer, hypervisor, and method are disclosed for allocating physical cores for maintaining an OS without changing the number of logical cores even if...
2016/0357646 MULTIPLE MEMORY FORMAT STORAGE IN A STORAGE NETWORK
A method includes sending a data retrieval request regarding a data segment of a data object to redundant array of independent disk (RAID) memory and to...
2016/0357645 HARDWARE-ASSISTED APPLICATION CHECKPOINTING AND RESTORING
Technologies for hardware-assisted application checkpointing include a computing device having a processor with hardware checkpoint support. In response to...
2016/0357644 SYSTEM AND METHOD FOR DATACENTERS DISASTER RECOVERY
Method and system for asynchronously dispersing Disaster Recovery (DR) enabling data between a plurality of storage sites. The method comprises: receiving, at...
2016/0357643 CROSS SITE RECOVERY OF A VM
Restoring a virtual machine is disclosed. An indication of the virtual machine of a primary site to be restored at a remote site using a copy stored at the...
2016/0357642 MULTI-RPO DATA PROTECTION
A system for disaster recovery including a controller (i) for controlling bandwidth usage of a disaster recovery system in accordance with a plurality of...
2016/0357641 CAPTURING POST-SNAPSHOT QUIESCENCE WRITES IN AN IMAGE BACKUP
Capturing post-snapshot quiescence writes in an image backup. In one example embodiment, a method for capturing post-snapshot quiescence writes in an image...
2016/0357640 CAPTURING POST-SNAPSHOT QUIESCENCE WRITES IN A LINEAR IMAGE BACKUP CHAIN
Capturing post-snapshot quiescence writes in a linear image backup chain. In one example embodiment, a method for capturing post-snapshot quiescence writes in...
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