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Patent # Description
2016/0365359 SEMICONDUCTOR DEVICE
A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first...
2016/0365358 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for...
2016/0365357 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
A semiconductor memory device includes a stack including gate electrodes and insulating layers that are alternately and repeatedly stacked on a substrate. A...
2016/0365356 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A semiconductor device includes a substrate, a stack structure, peripheral gate structures and residual spacers. The substrate includes a cell array region and...
2016/0365355 METHODS OF FORMING MEMORY ARRAYS
A method of forming a memory array includes filling a circular hole that is lined with a charge trapping layer with a conductor, forming a first slot and a...
2016/0365354 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
There are provided a semiconductor device and a method of manufacturing the same. A semiconductor device includes a memory block having local lines; a...
2016/0365353 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
In accordance with an embodiment, a manufacturing method of a semiconductor device includes forming a first film on an inner wall of a hole in a stack on a...
2016/0365352 PASSIVE DEVICES FOR INTEGRATION WITH THREE-DIMENSIONAL MEMORY DEVICES
A three dimensional memory device includes a memory device region containing a plurality of non-volatile memory devices, a peripheral device region containing...
2016/0365351 PASSIVE DEVICES FOR INTEGRATION WITH THREE-DIMENSIONAL MEMORY DEVICES
A three dimensional memory device includes a memory device region containing a plurality of non-volatile memory devices, a peripheral device region containing...
2016/0365350 METHOD FOR FORMING A SPLIT-GATE FLASH MEMORY CELL DEVICE WITH A LOW POWER LOGIC DEVICE
A method of manufacturing an embedded flash memory device is provided. A pair of gate stacks are formed spaced over a semiconductor substrate, and including...
2016/0365349 STACKED BIT LINE DUAL WORD LINE NONVOLATILE MEMORY
An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level...
2016/0365348 SPACER CHAMFERING GATE STACK SCHEME
A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are...
2016/0365347 ALTERNATIVE THRESHOLD VOLTAGE SCHEME VIA DIRECT METAL GATE PATTERNING FOR HIGH PERFORMANCE CMOS FinFETs
Multiple gate stack portions are formed in a gate cavity by direct metal gate patterning to provide FinFETs having different threshold voltages. The different...
2016/0365346 SPACER CHAMFERING GATE STACK SCHEME
A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are...
2016/0365345 Wrap Around Silicide for FinFETs
A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the...
2016/0365344 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
The present invention provides a semiconductor structure, including a substrate having a first fin structure and a second fin structure disposed thereon, a...
2016/0365343 GATE STRUCTURE WITH INSULATING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a gate...
2016/0365342 MANUFACTURING OF SELF ALIGNED INTERCONNECTION ELEMENTS FOR 3D INTEGRATED CIRCUITS
Method for making connection elements between two different levels of components in a 3D integrated circuit including steps of: forming a lateral insulating...
2016/0365341 HIGH BREAKDOWN VOLTAGE III-N DEPLETION MODE MOS CAPACITORS
III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to...
2016/0365340 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE
a method of fabricating a semiconductor device is described below. The method includes stacking a plurality of semiconductor chips on each of regions in a...
2016/0365339 OPTICAL MODULE INTEGRATED PACKAGE
A an optical module integrated package includes a substrate, a light-receiving chip mounted in a light-receiving region of the substrate, an electronic...
2016/0365338 OPTICAL APPARATUS
An optical apparatus includes a substrate 1, a wiring pattern 8 formed on the substrate 1, a light-receiving element 3 and a light-emitting element 2 provided...
2016/0365337 LIGHTING DEVICE
A lighting device includes a plurality of light-emitting diodes including a first light-emitting diode with a non-rectangular shape in a top view, a submount...
2016/0365336 SEMICONDUCTOR DEVICE INCLUDING PROTECTIVE FILM OVER A SUBSTRATE
A semiconductor device includes a first semiconductor chip including an inorganic protective film, a second semiconductor chip including an organic protective...
2016/0365335 SEMICONDUCTOR CHIP WITH REDUNDANT THRU-SILICON-VIAS
A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive...
2016/0365334 PACKAGE-ON-PACKAGE ASSEMBLY AND METHOD FOR MANUFACTURING THE SAME
A package-on-package assembly includes a bottom die package and a top die package mounted on the bottom die package. The bottom die package includes an...
2016/0365333 Semiconductor Module, Semiconductor Module Arrangement and Method for Operating a Semiconductor Module
A semiconductor module includes a first semiconductor switch, a second semiconductor switch, a circuit carrier arrangement and a non-ceramic dielectric...
2016/0365332 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A method of manufacturing a semiconductor structure, comprising: receiving a first substrate including a first surface, a second surface opposite to the first...
2016/0365331 WIRE TENSIONER
A wire tensioner has a wire passage through which a wire is inserted. The wire passage include: an inlet through which a compressed gas enters; a first outlet...
2016/0365330 METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND WIRE-BONDING APPARATUS
A method of manufacturing a semiconductor device is provided. A bonding tool with a wire tail extending out of the tip thereof is lowered to bring the tip of...
2016/0365329 CHIP-ON-CHIP STRUCTURE AND METHODS OF MANUFACTURE
Sintered connection structures and methods of manufacture are disclosed. The method includes placing a powder on a substrate and sintering the powder to form a...
2016/0365328 CHIP-ON-CHIP STRUCTURE AND METHODS OF MANUFACTURE
Sintered connection structures and methods of manufacture are disclosed. The method includes placing a powder on a substrate and sintering the powder to form a...
2016/0365327 WIRING BOARD AND ELECTRONIC COMPONENT DEVICE
A wiring board includes: an insulating layer; a pad including: an upper surface; a lower surface opposite to the upper surface; and a side surface between the...
2016/0365326 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device comprises a semiconductor chip which includes at least one gate structure on a substrate, the gate structure including a first region, a...
2016/0365325 GRID ARRAY CONNECTION DEVICE AND METHOD
A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such...
2016/0365324 METHOD OF MANUFACTURING WAFER LEVEL PACKAGE
Provided is a method of manufacturing a wafer level package. The method includes forming a repassivation layer that encapsulates a plurality of semiconductor...
2016/0365323 ELECTRONIC DEVICES WITH ATTACHED DIE STRUCTURES AND METHODS OF FORMATION OF SUCH DEVICES
An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a...
2016/0365322 Substrate Design with Balanced Metal and Solder Resist Density
A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer...
2016/0365321 METHOD AND APPARATUS FOR USING UNIVERSAL CAVITY WAFER IN WAFER LEVEL PACKAGING
An electronics module assembly is described herein that packages dies using a universal cavity wafer that is independent of electronics module design. In one...
2016/0365320 SEMICONDUCTOR DEVICE
A semiconductor device includes a cooling plate made of metal, one or more laminated substrates each formed by laminating a circuit board, an insulating board,...
2016/0365319 WAFER LEVEL PACKAGE
A water level package includes a substrate, a plurality of semiconductor chips mounted on the substrate, and molding members that contact the substrate and the...
2016/0365318 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes an integrated circuit, at least one outer seal ring, and at least one inner seal ring. The outer seal ring surrounds the...
2016/0365317 METHOD AND APPARATUS FOR FORMING EMI SHIELDING LAYERS ON SEMICONDUCTOR PACKAGES
A method and apparatus for EMI shielding of an electronic package is described. The method includes applying a patterned package support to a transport tray,...
2016/0365316 SEMICONDUCTOR DEVICE, ELECTRONIC APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the...
2016/0365315 SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF
A semiconductor process includes the following steps. Metal patterns are formed on a first dielectric layer. A modifiable layer is formed to cover the metal...
2016/0365314 CAPACITORS
Back end of the line (BEOL) capacitors and methods of manufacture are provided. The method includes forming wiring lines on a substrate, with spacing between...
2016/0365313 MEMORY DEVICE STRUCTURE AND FABRICATING METHOD THEREOF
The disclosed subject matter provides a memory device structure and a fabricating method thereof. The memory device structure includes a substrate including a...
2016/0365312 CAPACITORS
Back end of the line (BEOL) capacitors and methods of manufacture are provided. The method includes forming wiring lines on a substrate, with spacing between...
2016/0365311 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES WITH COMBINED ARRAY AND PERIPHERY PATTERNING IN SELF-ALIGNED...
Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. A method may incorporate the patterning of...
2016/0365310 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES WITH COMBINED ARRAY AND PERIPHERY PATTERNING IN SELF-ALIGNED...
Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. A method may incorporate the patterning of...
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