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SELF-ALIGNED BOTTOM UP GATE CONTACT AND TOP DOWN SOURCE-DRAIN CONTACT
STRUCTURE IN THE PREMETALLIZATION...
An integrated circuit includes a source-drain region, a channel region adjacent to the source-drain region, a gate structure extending over the channel region...
CHIP ON FILM UNIT
In the technical field of liquid crystal technology, a chip on film unit is provided. The chip on film unit comprises a soft dielectric layer, a plurality of...
A semiconductor device in which the electrical connection is established using conductive pins and a printed wiring board, wherein the printed wiring board is...
PACKAGE MODULE AND METHOD OF FABRICATING THE SAME
A method of fabricating a package module includes placing a pin frame having plural pins on a circuit substrate; bonding the pins to corresponding bonding...
LEAD FRAME WITH CONDUCTIVE CLIP FOR MOUNTING A SEMICONDUCTOR DIE WITH
REDUCED CLIP SHIFTING
A semiconductor assembly includes a semiconductor die comprising lower and upper electrical contacts. A lead frame having a lower die pad is electrically and...
Semiconductor Package with Embedded Output Inductor
In one implementation, a semiconductor package includes a control transistor and a sync transistor of a power converter switching stage attached over a first...
The semiconductor device improves heat dissipation by loading a diode and a MOSFET or IGBT in a single package. A drain electrode disposed on a rear surface of...
REVERSED BUILD-UP SUBSTRATE FOR 2.5D
A method of making an assembly can include forming a circuit structure defining front and rear surfaces, and forming a substrate onto the rear surface. The...
A cooler (1) includes: a fin (20) having a coolant inflow port (110a); and a nozzle (10) configured to eject the supplied coolant toward the coolant inflow...
Coolant Distribution Structure For Monolithic Microwave Integrated
A coolant distribution structure for an MMIC having: an input/output layer with an input port for receiving a coolant for transmission to coolant channels in...
A semiconductor device includes a semiconductor element, a substrate, a lead, and a sealing resin member. The semiconductor element has a first electrode and a...
In a semiconductor device, an insulating substrate housed in an housing opening portion of a resin case includes an insulating board, a first metal layer...
TIM STRAIN MITIGATION IN ELECTRONIC MODULES
A heat spreading lid including a lid body and a wing portion having a thermal interface material disposed on the wing portion such that the wing portion...
Electronic Devices with Increased Creepage Distances
A device includes an encapsulation material and a first lead and a second lead protruding out of a surface of the encapsulation material. A recess extends into...
SEMICONDUCTOR ARRANGEMENT, SEMICONDUCTOR SYSTEM AND METHOD OF FORMING A
A semiconductor arrangement is provided. The semiconductor arrangement may include an electrically conductive plate having a surface, a plurality of power...
A semiconductor device including a power transistor is prevented from being broken. A cathode of a temperature sensing diode and a source of a power MOSFET are...
METHOD FOR EVALUATING SEMICONDUCTOR SUBSTRATE
The present invention provides a method for evaluating a semiconductor substrate subjected to a defect recovery heat treatment to recover a crystal defect in...
METHOD AND STRUCTURE FOR ENABLING CONTROLLED SPACER RIE
A method and structure to enable reliable dielectric spacer endpoint detection by utilizing a sacrificial spacer fin are provided. The sacrificial spacer fin...
VERTICALLY INTEGRATED MEMORY CELL
A method of forming a vertically integrated memory cell including a deep trench extending into a substrate, a trench capacitor located within the deep trench,...
SPACER CHAMFERING GATE STACK SCHEME
A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are...
Method for Manufacturing A Dual Work Function Semiconductor Device and the
Semiconductor Device Made Thereof
A method for manufacturing a dual work function semiconductor device includes forming a first silicon oxide layer on a substrate and forming a first...
DUMMY GATE USED AS INTERCONNECTION AND METHOD OF MAKING THE SAME
Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor...
SELF-ALIGNED HARD MASK FOR EPITAXY PROTECTION
A method includes isolating a first and at least a second region on a semiconductor substrate, and forming one or more devices on each of the first and at...
SEMICONDUCTOR FINS FOR FINFET DEVICES AND SIDEWALL IMAGE TRANSFER (SIT)
PROCESSES FOR MANUFACTURING THE SAME
A method of forming a semiconductor structure includes providing a semiconductor substrate, forming at least one precursor semiconductor fin from the...
SELF-ALIGNED LOW DEFECT SEGMENTED III-V FINFET
A method includes forming one or more fin structures on a substrate, the one or more fin structures comprising a first material comprising a first lattice...
Fabrication Methodology For Optoelectronic Integrated Circuits
A method of forming an integrated circuit employs a plurality of layers formed on a substrate including i) bottom n-type ohmic contact layer, ii) p-type...
ETCH-RESISTANT WATER SOLUBLE MASK FOR HYBRID WAFER DICING USING LASER
SCRIBING AND PLASMA ETCH
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor...
Carbon Layer and Method of Manufacture
A system and method for manufacturing a carbon layer is provided. An embodiment comprises depositing a first metal layer on a substrate, the substrate...
FLIP CHIP ALIGNMENT MARK EXPOSING METHOD ENABLING WAFER LEVEL UNDERFILL
Alignment marks on a semiconductor device surface are exposed and exposed surfaces cleaned after an obscuring coating is applied over the surface and marks....
CHEMOEPITAXY ETCH TRIM USING A SELF ALIGNED HARD MASK FOR METAL LINE TO
A method of forming metal lines that are aligned to underlying metal features that includes forming a neutral layer atop a hardmask layer that is overlying a...
METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING CONTACT STRUCTURES
Provided is a method of fabricating a semiconductor device, the method including forming interconnection structures extending parallel to each other on a...
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
It is to provide a manufacturing method of a semiconductor device including the following step of: preparing a semiconductor substrate having a silicon nitride...
SACRIFICIAL AMORPHOUS SILICON HARD MASK FOR BEOL
A starting metallization structure for electrically coupling one or more underlying semiconductor devices, the structure including a bottom layer of dielectric...
METHOD OF FORMING AN INTERCONNECT STRUCTURE FOR A SEMICONDUCTOR DEVICE
Methods of semiconductor device fabrication are provided including those that provide a substrate having a plurality of trenches disposed in a dielectric layer...
FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE WITH INTERCONNECT
A semiconductor device structure is provided. The semiconductor device structure includes a first metal layer formed over a substrate and an interconnect...
METHODS OF FABRICATING SEMICONDUCTOR DEVICE
Methods of fabricating a semiconductor device include forming a gate pattern on a substrate, forming spacers to cover both sidewalls of the gate pattern,...
METHOD FOR MANUFACTURING BONDED WAFER
A method for manufacturing a bonded wafer, includes: ion-implanting a gas ion such as a hydrogen ion from a surface of a bond wafer, thereby forming an...
METHOD OF FORMING SHALLOW TRENCH ISOLATION (STI) STRUCTURES
A method of forming a trench isolation (e.g., an STI) for an integrated circuit includes forming a pad oxide layer and then a nitride layer over a...
FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE WITH INTERCONNECT
A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first metal layer formed over a...
WAFER PROCESSING METHOD
A method of processing a wafer includes coating the front side of the wafer with a water-soluble liquid resin to form a thin film; fixing the wafer to a...
WAFER CARRIER FOR SMALLER WAFERS AND WAFER PIECES
Embodiments described herein relate to an apparatus and method for securing and transferring substrates. A substrate carrier, having one or more electrostatic...
Module Testing Utilizing Wafer Probe Test Equipment
A module plate is provided for use with a wafer handler and testing mechanism. The module plate has a diameter equivalent to an integrated circuit wafer and a...
BONDING APPARATUS AND BONDING METHOD
A bonding apparatus, which includes: an intermediate stage; a transfer unit configured to transfer a semiconductor chip and to place the semiconductor chip on...
PURGE APPARATUS AND PURGE METHOD
A nozzle prevents obstruction of alignment of a container without using an actuator. When the nozzle contacts the container before an alignment member does,...
WAFER SHIPPER WITH STACKED SUPPORT RINGS
A wafer shipper utilizing wafer support rings for supporting individual wafers therein. The wafer support rings can support wafers of various thicknesses...
SUBSTRATE PROCESSING APPARATUS
The present invention provides a technique in which a reduction in yield rate caused by particles occurring in the processing furnace is suppressed. The...
EFFLUENT CONTROL SYSTEM
An apparatus, method, and system for collecting data related to effluent emitted from tools in semiconductor fabrication facilities using one or more sensors...
SEMICONDUCTOR FABRICATION FACILITY DATA COLLECTION SYSTEM
A system and method for collecting and analyzing real-time data generated by different semiconductor fabrication tools in a semiconductor fabrication facility,...
PLASMA ETCHING DEVICE WITH DOPED QUARTZ SURFACES
An apparatus for processing a substrate is provided. A processing chamber is provided. A substrate support for supporting the substrate is within the...
SUBSTRATE PROCESSING APPARATUS
A substrate processing apparatus has a labyrinth around a processing liquid nozzle above a nozzle gap, and a seal gas is supplied to the labyrinth to seal the...