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NUCLEAR FUSOR APPARATUS
The present patent application discloses a nuclear fusor apparatus, which includes a magnetically conductive spherical shell, a solid iron ball, a plurality of...
MEMORY SYSTEM INCLUDING PLURALITY OF MEMORY REGIONS AND METHOD OF
OPERATING THE SAME
A method of a memory system including memory regions includes performing error corrections for chunks in each of the memory regions, and computing trust levels...
METHOD AND APPARATUS FOR TESTING INTEGRATED CIRCUIT
An integrated circuit (IC) having a memory for storing data also has a memory built in self-test (MBIST) unit coupled to the memory for testing an operation of...
BUILT-IN SELF-TEST (BIST) CIRCUIT AND ASSOCIATED BIST METHOD FOR EMBEDDED
Disclosed is a chip with a built-in self-test (BIST) circuit that incorporates a BIST engine that tests memories in parallel and that, prior to testing,...
INITIAL ENUMERATION OF EMPTY ENDPOINT SLOTS USING ENDPOINT EMULATION
Embodiments of the present disclosure are directed to a system comprising a processing unit executing an enumeration process over a high performance I/O...
SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a memory cell, a sense amplifier connected to the memory cell, a first data latch that is connected to the sense...
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH PERFORMS IMPROVED ERASE
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control unit. The memory cell array includes a...
PROGRAMMING METHODS AND MEMORIES
A method of programming a memory includes boosting a channel voltage while a first portion of a plurality of increasing programming pulses is applied to a...
Systems and Methods for Dynamically Programming a Flash Memory Device
The present inventions are related to systems and methods for storing data, and more particularly to systems and methods for writing data to a storage device.
SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM
A semiconductor memory device includes a memory cell, and a control circuit configured to execute a writing operation on the memory cell in response to a write...
NONVOLATILE MEMORY DEVICE AND WORDLINE DRIVING METHOD THEREOF
According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array, an address decoder, an input/output circuit,...
EEPROM MEMORY CELL GATE CONTROL SIGNAL GENERATING CIRCUIT
An EEPROM memory cell gate control signal generating circuit, which includes a high-voltage row decoding circuit and a plurality of word selection circuits;...
HIGH SPEED, HIGH VOLTAGE TOLERANT CIRCUITS IN FLASH PATH
A circuit includes a first word line coupled to a non-volatile memory (NVM) cell. A first path includes a first inverter and a transistor. The transistor is...
TCAM STRUCTURES WITH REDUCED POWER SUPPLY NOISE
A ternary content addressable memory (TCAM) structure may activate individual groups of subarrays in the TCAM structure, during a non-search mode, at...
Non-Volatile Static RAM and Method of Operation Thereof
A memory device and array which includes a static random access memory (SRAM) circuit coupled to a non-volatile circuit, such as a ferroelectric-RAM (F-RAM)...
SEMICONDUCTOR MEMORY DEVICE
Included are memory cells each including a resistance change element and a control circuit. The circuit performs an On writing process for applying, to the...
SEMICONDUCTOR STORAGE DEVICE WITH VOLTAGE GENERATOR
According to one embodiment, a semiconductor storage device includes: a memory cell including a variable resistance element; a bit line coupled to the memory...
MEMORY CELLS HAVING A PLURALITY OF RESISTANCE VARIABLE MATERIALS
Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an...
APPARATUSES, DEVICES AND METHODS FOR SENSING A SNAPBACK EVENT IN A CIRCUIT
Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric...
SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL AND SENSE AMPLIFER, AND IC CARD
INCLUDING SEMICONDUCTOR DEVICE
A semiconductor device includes a memory cell; circuitry that generates a reference voltage; and a sense amplifier including a first input terminal ...
CIRCUIT TO IMPROVE SRAM STABILITY
Approaches for stability of cells in a Static Random Access Memory (SRAM) array are provided. A circuit includes a precharging circuit configured to precharge...
Method of Managing Data of Storage Devices Responsive to Temperature
Methods of managing data of a storage device responsive to temperature can include measuring a temperature of the storage device, changing a duration of a...
Pre-Emphasis and Equalization for DRAM
The present disclosure is directed to apparatuses and methods to pre-compensate and/or post-compensate for inter-symbol interference (ISI). The apparatuses and...
STACKED SEMICONDUCTOR DEVICE
A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with...
Multiple Gating Modes and Half-Frequency Dynamic Calibration for DDR
Circuits and methods are described for a DDR memory controller where two different DQS gating modes are utilized. These gating modes together ensure that the...
A memory system is disclosed, which relates to a technology for reducing current consumption needed to perform a refresh operation in a Dual In-line Memory...
NON-VOLATILE MEMORY DEVICE
A non-volatile memory device according to an embodiment includes a first conductive layer, a second conductive layer including metal nitride, the metal nitride...
MAGNETORESISTIVE MEMORY DEVICE
A magnetoresistive memory device includes a variable resistance element and a read circuit. The resistance element has a resistance state, which is one of...
MEMORY DEVICE WITH PARALLEL ODD AND EVEN COLUMN ACCESS AND METHODS THEREOF
A memory device includes: a plurality of first lines; a plurality of second lines; a plurality of bank groups each including a predetermined number of banks;...
Current-Mode Sense Amplifier
A current sense amplifier is provided comprising a reference current input terminal, a control line input terminal, a sense current input terminal and a first...
SIMULATING ACCESS LINES
Examples of the present disclosure provide apparatuses and methods for simulating access lines in a memory. An example method can include receiving a first...
APPARATUSES AND METHODS FOR COMPENSATING FOR PROCESS, VOLTAGE, AND
TEMPERATURE VARIATION IN A MEMORY
Systems and methods are described for compensating for variations in process, voltage, temperature, or combinations thereof in an apparatus. An example...
MEMORY SYSTEM AND OPERATING METHOD THEREOF
There are provided a memory system and an operating method thereof. A memory system includes a memory device suitable for storing data therein; and a memory...
REAL-TIME POSITIONING OF CURRENT-PLAYING-POSITION MARKER ON PROGRESS BAR
AND INDEX FILE GENERATION FOR...
Embodiments are directed towards presenting a current-playing-position marker on a progress bar along with real time content. An initial timeline value of the...
RECORDING DEVICE, RECORDING METHOD, AND NON-TRANSITORY RECORDING MEDIUM
A recording device includes an imaging unit that takes a video, a recording time conversion processor that converts a frame rate of specified video data in the...
VIDEO EDITING METHOD USING PARTICIPANT SHARING
A video editing method using participant sharing is described. In one embodiment, the method comprises determining existence of one or both of signal data and...
METHOD AND ELECTRONIC DEVICE FOR VIDEO DEFINITION SWITCHING
Disclosed are a method and electronic device for video definition switching. The method comprises: loading a first fragment file of a first definition video...
VIDEO EDITING SYSTEM WITH MULTI-STAGE CONTROL TO GENERATE CLIPS
A video editing system and method with multi-stage control to generate clips are described. In one embodiment, the video editing system comprises editing...
Game Video Processing Systems and Methods
In some embodiments, a video processing system may be configured to process a video of a sporting event or match to determine a start point and an end point of...
VIDEO EDITING SYSTEM FOR GENERATING MULTIPLE FINAL CUT CLIPS
A video editing apparatus and method for generating multiple final cut clips is described. In one embodiment, a video editing system comprises editing...
VIDEO EDITING SYSTEM WITH MULTI-STAKEHOLDER, MULTI-STAGE CONTROL
A video editing system and method using multi-stakeholder, multi-stage control are described. In one embodiment, the video editing system comprises editing...
VIDEO EDITING SYSTEM WITH MULTI-STAKEHOLDER CONTROL
A video editing system and method using multi-stakeholder control are described. In one embodiment, the video editing system comprises editing processing logic...
METHOD FOR PROCESSING CAPTURED VIDEO DATA BASED ON CAPTURE DEVICE
Methods for processing captured video data based on capture device orientation are described. In one embodiment, the method comprises capturing video data with...
VIDEO EDITING APPARATUS WITH PARTICIPANT SHARING
A Video Editing Apparatus with Participant Sharing is described. In one embodiment, the video editing system comprises a memory to store instructions and video...
VIDEO EDITING SYSTEM AND METHOD USING TIME-BASED HIGHLIGHT IDENTIFICATION
A video editing apparatus and method using time-based highlight identification are described. In one embodiment, a video editing apparatus comprises a memory...
VIDEO EDITING SYSTEM AND METHOD USING MACHINE LEARNING
A video editing system and method using machine learning are described. In one embodiment, the video editing system comprises editing processing logic...
PLAYBACK DEVICE, PLAYBACK METHOD, AND NON-TRANSITORY RECORDING MEDIUM
A playback device includes a playback controller that sets a scene with a higher level of importance at a lower playback speed and sets a scene with a lower...
SYSTEMS AND METHODS FOR DECODING USING RUN-LENGTH LIMITED (RLL) CODES
A method of decoding a codeword that satisfies a k constraint into output data includes, using a decoder of a hard disk drive system, converting each bit of...
MAGNETIZATION MAP OF A STORAGE MEDIUM
To read data from a storage medium, a magnetization map of the data stored on at least one portion of the storage medium is obtained. The magnetization map is...
SYMBOL TIMING RECOVERY SCHEME FOR PARALLEL RECORDING CHANNEL SYSTEMS
An apparatus includes a loop filter that receives a plurality of input signals. Each of the input signals is based on a different timing error detector output...